Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 1 | /* |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 7 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 8 | #include <asm_macros.S> |
Jan Dabros | fa01598 | 2019-12-02 13:30:03 +0100 | [diff] [blame] | 9 | #include <assert_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 10 | #include <context.h> |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 11 | #include <el3_common_macros.S> |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 12 | |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 13 | #if CTX_INCLUDE_EL2_REGS |
| 14 | .global el2_sysregs_context_save |
| 15 | .global el2_sysregs_context_restore |
| 16 | #endif |
| 17 | |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 18 | .global el1_sysregs_context_save |
| 19 | .global el1_sysregs_context_restore |
| 20 | #if CTX_INCLUDE_FPREGS |
| 21 | .global fpregs_context_save |
| 22 | .global fpregs_context_restore |
| 23 | #endif |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 24 | .global save_gp_pmcr_pauth_regs |
| 25 | .global restore_gp_pmcr_pauth_regs |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 26 | .global save_and_update_ptw_el1_sys_regs |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 27 | .global el3_exit |
| 28 | |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 29 | #if CTX_INCLUDE_EL2_REGS |
| 30 | |
| 31 | /* ----------------------------------------------------- |
| 32 | * The following function strictly follows the AArch64 |
| 33 | * PCS to use x9-x17 (temporary caller-saved registers) |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 34 | * to save EL2 system register context. It assumes that |
| 35 | * 'x0' is pointing to a 'el2_sys_regs' structure where |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 36 | * the register context will be saved. |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 37 | * |
| 38 | * The following registers are not added. |
| 39 | * AMEVCNTVOFF0<n>_EL2 |
| 40 | * AMEVCNTVOFF1<n>_EL2 |
| 41 | * ICH_AP0R<n>_EL2 |
| 42 | * ICH_AP1R<n>_EL2 |
| 43 | * ICH_LR<n>_EL2 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 44 | * ----------------------------------------------------- |
| 45 | */ |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 46 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 47 | func el2_sysregs_context_save |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 48 | mrs x9, actlr_el2 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 49 | mrs x10, afsr0_el2 |
| 50 | stp x9, x10, [x0, #CTX_ACTLR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 51 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 52 | mrs x11, afsr1_el2 |
| 53 | mrs x12, amair_el2 |
| 54 | stp x11, x12, [x0, #CTX_AFSR1_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 55 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 56 | mrs x13, cnthctl_el2 |
| 57 | mrs x14, cnthp_ctl_el2 |
| 58 | stp x13, x14, [x0, #CTX_CNTHCTL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 59 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 60 | mrs x15, cnthp_cval_el2 |
| 61 | mrs x16, cnthp_tval_el2 |
| 62 | stp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 63 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 64 | mrs x17, cntvoff_el2 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 65 | mrs x9, cptr_el2 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 66 | stp x17, x9, [x0, #CTX_CNTVOFF_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 67 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 68 | mrs x11, elr_el2 |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 69 | #if CTX_INCLUDE_AARCH32_REGS |
| 70 | mrs x10, dbgvcr32_el2 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 71 | stp x10, x11, [x0, #CTX_DBGVCR32_EL2] |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 72 | #else |
| 73 | str x11, [x0, #CTX_ELR_EL2] |
| 74 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 75 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 76 | mrs x14, esr_el2 |
| 77 | mrs x15, far_el2 |
| 78 | stp x14, x15, [x0, #CTX_ESR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 79 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 80 | mrs x16, hacr_el2 |
| 81 | mrs x17, hcr_el2 |
| 82 | stp x16, x17, [x0, #CTX_HACR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 83 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 84 | mrs x9, hpfar_el2 |
| 85 | mrs x10, hstr_el2 |
| 86 | stp x9, x10, [x0, #CTX_HPFAR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 87 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 88 | mrs x11, ICC_SRE_EL2 |
| 89 | mrs x12, ICH_HCR_EL2 |
| 90 | stp x11, x12, [x0, #CTX_ICC_SRE_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 91 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 92 | mrs x13, ICH_VMCR_EL2 |
| 93 | mrs x14, mair_el2 |
| 94 | stp x13, x14, [x0, #CTX_ICH_VMCR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 95 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 96 | mrs x15, mdcr_el2 |
| 97 | mrs x16, PMSCR_EL2 |
| 98 | stp x15, x16, [x0, #CTX_MDCR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 99 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 100 | mrs x17, sctlr_el2 |
| 101 | mrs x9, spsr_el2 |
| 102 | stp x17, x9, [x0, #CTX_SCTLR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 103 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 104 | mrs x10, sp_el2 |
| 105 | mrs x11, tcr_el2 |
| 106 | stp x10, x11, [x0, #CTX_SP_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 107 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 108 | mrs x12, tpidr_el2 |
| 109 | mrs x13, ttbr0_el2 |
| 110 | stp x12, x13, [x0, #CTX_TPIDR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 111 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 112 | mrs x14, vbar_el2 |
| 113 | mrs x15, vmpidr_el2 |
| 114 | stp x14, x15, [x0, #CTX_VBAR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 115 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 116 | mrs x16, vpidr_el2 |
| 117 | mrs x17, vtcr_el2 |
| 118 | stp x16, x17, [x0, #CTX_VPIDR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 119 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 120 | mrs x9, vttbr_el2 |
| 121 | str x9, [x0, #CTX_VTTBR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 122 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 123 | #if CTX_INCLUDE_MTE_REGS |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 124 | mrs x10, TFSR_EL2 |
| 125 | str x10, [x0, #CTX_TFSR_EL2] |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 126 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 127 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 128 | #if ENABLE_MPAM_FOR_LOWER_ELS |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 129 | mrs x9, MPAM2_EL2 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 130 | mrs x10, MPAMHCR_EL2 |
| 131 | stp x9, x10, [x0, #CTX_MPAM2_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 132 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 133 | mrs x11, MPAMVPM0_EL2 |
| 134 | mrs x12, MPAMVPM1_EL2 |
| 135 | stp x11, x12, [x0, #CTX_MPAMVPM0_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 136 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 137 | mrs x13, MPAMVPM2_EL2 |
| 138 | mrs x14, MPAMVPM3_EL2 |
| 139 | stp x13, x14, [x0, #CTX_MPAMVPM2_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 140 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 141 | mrs x15, MPAMVPM4_EL2 |
| 142 | mrs x16, MPAMVPM5_EL2 |
| 143 | stp x15, x16, [x0, #CTX_MPAMVPM4_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 144 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 145 | mrs x17, MPAMVPM6_EL2 |
| 146 | mrs x9, MPAMVPM7_EL2 |
| 147 | stp x17, x9, [x0, #CTX_MPAMVPM6_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 148 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 149 | mrs x10, MPAMVPMV_EL2 |
| 150 | str x10, [x0, #CTX_MPAMVPMV_EL2] |
| 151 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 152 | |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 153 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 154 | #if ARM_ARCH_AT_LEAST(8, 6) |
| 155 | mrs x11, HAFGRTR_EL2 |
| 156 | mrs x12, HDFGRTR_EL2 |
| 157 | stp x11, x12, [x0, #CTX_HAFGRTR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 158 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 159 | mrs x13, HDFGWTR_EL2 |
| 160 | mrs x14, HFGITR_EL2 |
| 161 | stp x13, x14, [x0, #CTX_HDFGWTR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 162 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 163 | mrs x15, HFGRTR_EL2 |
| 164 | mrs x16, HFGWTR_EL2 |
| 165 | stp x15, x16, [x0, #CTX_HFGRTR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 166 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 167 | mrs x17, CNTPOFF_EL2 |
| 168 | str x17, [x0, #CTX_CNTPOFF_EL2] |
| 169 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 170 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 171 | #if ARM_ARCH_AT_LEAST(8, 4) |
| 172 | mrs x9, cnthps_ctl_el2 |
| 173 | mrs x10, cnthps_cval_el2 |
| 174 | stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 175 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 176 | mrs x11, cnthps_tval_el2 |
| 177 | mrs x12, cnthvs_ctl_el2 |
| 178 | stp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 179 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 180 | mrs x13, cnthvs_cval_el2 |
| 181 | mrs x14, cnthvs_tval_el2 |
| 182 | stp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 183 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 184 | mrs x15, cnthv_ctl_el2 |
| 185 | mrs x16, cnthv_cval_el2 |
| 186 | stp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 187 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 188 | mrs x17, cnthv_tval_el2 |
| 189 | mrs x9, contextidr_el2 |
| 190 | stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 191 | |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 192 | #if CTX_INCLUDE_AARCH32_REGS |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 193 | mrs x10, sder32_el2 |
| 194 | str x10, [x0, #CTX_SDER32_EL2] |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 195 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 196 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 197 | mrs x11, ttbr1_el2 |
| 198 | str x11, [x0, #CTX_TTBR1_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 199 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 200 | mrs x12, vdisr_el2 |
| 201 | str x12, [x0, #CTX_VDISR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 202 | |
Arunachalam Ganapathy | dd3ec7e | 2020-05-28 11:57:09 +0100 | [diff] [blame^] | 203 | #if CTX_INCLUDE_NEVE_REGS |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 204 | mrs x13, vncr_el2 |
| 205 | str x13, [x0, #CTX_VNCR_EL2] |
Arunachalam Ganapathy | dd3ec7e | 2020-05-28 11:57:09 +0100 | [diff] [blame^] | 206 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 207 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 208 | mrs x14, vsesr_el2 |
| 209 | str x14, [x0, #CTX_VSESR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 210 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 211 | mrs x15, vstcr_el2 |
| 212 | str x15, [x0, #CTX_VSTCR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 213 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 214 | mrs x16, vsttbr_el2 |
| 215 | str x16, [x0, #CTX_VSTTBR_EL2] |
Olivier Deprez | 1962891 | 2020-03-20 14:22:05 +0100 | [diff] [blame] | 216 | |
| 217 | mrs x17, TRFCR_EL2 |
| 218 | str x17, [x0, #CTX_TRFCR_EL2] |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 219 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 220 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 221 | #if ARM_ARCH_AT_LEAST(8, 5) |
Olivier Deprez | 1962891 | 2020-03-20 14:22:05 +0100 | [diff] [blame] | 222 | mrs x9, scxtnum_el2 |
| 223 | str x9, [x0, #CTX_SCXTNUM_EL2] |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 224 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 225 | |
| 226 | ret |
| 227 | endfunc el2_sysregs_context_save |
| 228 | |
| 229 | /* ----------------------------------------------------- |
| 230 | * The following function strictly follows the AArch64 |
| 231 | * PCS to use x9-x17 (temporary caller-saved registers) |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 232 | * to restore EL2 system register context. It assumes |
| 233 | * that 'x0' is pointing to a 'el2_sys_regs' structure |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 234 | * from where the register context will be restored |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 235 | |
| 236 | * The following registers are not restored |
| 237 | * AMEVCNTVOFF0<n>_EL2 |
| 238 | * AMEVCNTVOFF1<n>_EL2 |
| 239 | * ICH_AP0R<n>_EL2 |
| 240 | * ICH_AP1R<n>_EL2 |
| 241 | * ICH_LR<n>_EL2 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 242 | * ----------------------------------------------------- |
| 243 | */ |
| 244 | func el2_sysregs_context_restore |
| 245 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 246 | ldp x9, x10, [x0, #CTX_ACTLR_EL2] |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 247 | msr actlr_el2, x9 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 248 | msr afsr0_el2, x10 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 249 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 250 | ldp x11, x12, [x0, #CTX_AFSR1_EL2] |
| 251 | msr afsr1_el2, x11 |
| 252 | msr amair_el2, x12 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 253 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 254 | ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] |
| 255 | msr cnthctl_el2, x13 |
| 256 | msr cnthp_ctl_el2, x14 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 257 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 258 | ldp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] |
| 259 | msr cnthp_cval_el2, x15 |
| 260 | msr cnthp_tval_el2, x16 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 261 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 262 | ldp x17, x9, [x0, #CTX_CNTVOFF_EL2] |
| 263 | msr cntvoff_el2, x17 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 264 | msr cptr_el2, x9 |
| 265 | |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 266 | #if CTX_INCLUDE_AARCH32_REGS |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 267 | ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] |
| 268 | msr dbgvcr32_el2, x10 |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 269 | #else |
| 270 | ldr x11, [x0, #CTX_ELR_EL2] |
| 271 | #endif |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 272 | msr elr_el2, x11 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 273 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 274 | ldp x14, x15, [x0, #CTX_ESR_EL2] |
| 275 | msr esr_el2, x14 |
| 276 | msr far_el2, x15 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 277 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 278 | ldp x16, x17, [x0, #CTX_HACR_EL2] |
| 279 | msr hacr_el2, x16 |
| 280 | msr hcr_el2, x17 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 281 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 282 | ldp x9, x10, [x0, #CTX_HPFAR_EL2] |
| 283 | msr hpfar_el2, x9 |
| 284 | msr hstr_el2, x10 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 285 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 286 | ldp x11, x12, [x0, #CTX_ICC_SRE_EL2] |
| 287 | msr ICC_SRE_EL2, x11 |
| 288 | msr ICH_HCR_EL2, x12 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 289 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 290 | ldp x13, x14, [x0, #CTX_ICH_VMCR_EL2] |
| 291 | msr ICH_VMCR_EL2, x13 |
| 292 | msr mair_el2, x14 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 293 | |
Max Shvetsov | 0c16abd | 2020-05-13 18:15:39 +0100 | [diff] [blame] | 294 | ldp x15, x16, [x0, #CTX_MDCR_EL2] |
| 295 | msr mdcr_el2, x15 |
| 296 | msr PMSCR_EL2, x16 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 297 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 298 | ldp x17, x9, [x0, #CTX_SCTLR_EL2] |
| 299 | msr sctlr_el2, x17 |
| 300 | msr spsr_el2, x9 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 301 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 302 | ldp x10, x11, [x0, #CTX_SP_EL2] |
| 303 | msr sp_el2, x10 |
| 304 | msr tcr_el2, x11 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 305 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 306 | ldp x12, x13, [x0, #CTX_TPIDR_EL2] |
| 307 | msr tpidr_el2, x12 |
| 308 | msr ttbr0_el2, x13 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 309 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 310 | ldp x13, x14, [x0, #CTX_VBAR_EL2] |
| 311 | msr vbar_el2, x13 |
| 312 | msr vmpidr_el2, x14 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 313 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 314 | ldp x15, x16, [x0, #CTX_VPIDR_EL2] |
| 315 | msr vpidr_el2, x15 |
| 316 | msr vtcr_el2, x16 |
| 317 | |
| 318 | ldr x17, [x0, #CTX_VTTBR_EL2] |
| 319 | msr vttbr_el2, x17 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 320 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 321 | #if CTX_INCLUDE_MTE_REGS |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 322 | ldr x9, [x0, #CTX_TFSR_EL2] |
| 323 | msr TFSR_EL2, x9 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 324 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 325 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 326 | #if ENABLE_MPAM_FOR_LOWER_ELS |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 327 | ldp x10, x11, [x0, #CTX_MPAM2_EL2] |
| 328 | msr MPAM2_EL2, x10 |
| 329 | msr MPAMHCR_EL2, x11 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 330 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 331 | ldp x12, x13, [x0, #CTX_MPAMVPM0_EL2] |
| 332 | msr MPAMVPM0_EL2, x12 |
| 333 | msr MPAMVPM1_EL2, x13 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 334 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 335 | ldp x14, x15, [x0, #CTX_MPAMVPM2_EL2] |
| 336 | msr MPAMVPM2_EL2, x14 |
| 337 | msr MPAMVPM3_EL2, x15 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 338 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 339 | ldp x16, x17, [x0, #CTX_MPAMVPM4_EL2] |
| 340 | msr MPAMVPM4_EL2, x16 |
| 341 | msr MPAMVPM5_EL2, x17 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 342 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 343 | ldp x9, x10, [x0, #CTX_MPAMVPM6_EL2] |
| 344 | msr MPAMVPM6_EL2, x9 |
| 345 | msr MPAMVPM7_EL2, x10 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 346 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 347 | ldr x11, [x0, #CTX_MPAMVPMV_EL2] |
| 348 | msr MPAMVPMV_EL2, x11 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 349 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 350 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 351 | #if ARM_ARCH_AT_LEAST(8, 6) |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 352 | ldp x12, x13, [x0, #CTX_HAFGRTR_EL2] |
| 353 | msr HAFGRTR_EL2, x12 |
| 354 | msr HDFGRTR_EL2, x13 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 355 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 356 | ldp x14, x15, [x0, #CTX_HDFGWTR_EL2] |
| 357 | msr HDFGWTR_EL2, x14 |
| 358 | msr HFGITR_EL2, x15 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 359 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 360 | ldp x16, x17, [x0, #CTX_HFGRTR_EL2] |
| 361 | msr HFGRTR_EL2, x16 |
| 362 | msr HFGWTR_EL2, x17 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 363 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 364 | ldr x9, [x0, #CTX_CNTPOFF_EL2] |
| 365 | msr CNTPOFF_EL2, x9 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 366 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 367 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 368 | #if ARM_ARCH_AT_LEAST(8, 4) |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 369 | ldp x10, x11, [x0, #CTX_CNTHPS_CTL_EL2] |
| 370 | msr cnthps_ctl_el2, x10 |
| 371 | msr cnthps_cval_el2, x11 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 372 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 373 | ldp x12, x13, [x0, #CTX_CNTHPS_TVAL_EL2] |
| 374 | msr cnthps_tval_el2, x12 |
| 375 | msr cnthvs_ctl_el2, x13 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 376 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 377 | ldp x14, x15, [x0, #CTX_CNTHVS_CVAL_EL2] |
| 378 | msr cnthvs_cval_el2, x14 |
| 379 | msr cnthvs_tval_el2, x15 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 380 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 381 | ldp x16, x17, [x0, #CTX_CNTHV_CTL_EL2] |
| 382 | msr cnthv_ctl_el2, x16 |
| 383 | msr cnthv_cval_el2, x17 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 384 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 385 | ldp x9, x10, [x0, #CTX_CNTHV_TVAL_EL2] |
| 386 | msr cnthv_tval_el2, x9 |
| 387 | msr contextidr_el2, x10 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 388 | |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 389 | #if CTX_INCLUDE_AARCH32_REGS |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 390 | ldr x11, [x0, #CTX_SDER32_EL2] |
| 391 | msr sder32_el2, x11 |
Arunachalam Ganapathy | dca591b | 2020-05-26 11:32:35 +0100 | [diff] [blame] | 392 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 393 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 394 | ldr x12, [x0, #CTX_TTBR1_EL2] |
| 395 | msr ttbr1_el2, x12 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 396 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 397 | ldr x13, [x0, #CTX_VDISR_EL2] |
| 398 | msr vdisr_el2, x13 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 399 | |
Arunachalam Ganapathy | dd3ec7e | 2020-05-28 11:57:09 +0100 | [diff] [blame^] | 400 | #if CTX_INCLUDE_NEVE_REGS |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 401 | ldr x14, [x0, #CTX_VNCR_EL2] |
| 402 | msr vncr_el2, x14 |
Arunachalam Ganapathy | dd3ec7e | 2020-05-28 11:57:09 +0100 | [diff] [blame^] | 403 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 404 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 405 | ldr x15, [x0, #CTX_VSESR_EL2] |
| 406 | msr vsesr_el2, x15 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 407 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 408 | ldr x16, [x0, #CTX_VSTCR_EL2] |
| 409 | msr vstcr_el2, x16 |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 410 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 411 | ldr x17, [x0, #CTX_VSTTBR_EL2] |
| 412 | msr vsttbr_el2, x17 |
Olivier Deprez | 1962891 | 2020-03-20 14:22:05 +0100 | [diff] [blame] | 413 | |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 414 | ldr x9, [x0, #CTX_TRFCR_EL2] |
| 415 | msr TRFCR_EL2, x9 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 416 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 417 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 418 | #if ARM_ARCH_AT_LEAST(8, 5) |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 419 | ldr x10, [x0, #CTX_SCXTNUM_EL2] |
| 420 | msr scxtnum_el2, x10 |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 421 | #endif |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 422 | |
| 423 | ret |
| 424 | endfunc el2_sysregs_context_restore |
| 425 | |
| 426 | #endif /* CTX_INCLUDE_EL2_REGS */ |
| 427 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 428 | /* ------------------------------------------------------------------ |
| 429 | * The following function strictly follows the AArch64 PCS to use |
| 430 | * x9-x17 (temporary caller-saved registers) to save EL1 system |
| 431 | * register context. It assumes that 'x0' is pointing to a |
| 432 | * 'el1_sys_regs' structure where the register context will be saved. |
| 433 | * ------------------------------------------------------------------ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 434 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 435 | func el1_sysregs_context_save |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 436 | |
| 437 | mrs x9, spsr_el1 |
| 438 | mrs x10, elr_el1 |
| 439 | stp x9, x10, [x0, #CTX_SPSR_EL1] |
| 440 | |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 441 | #if !ERRATA_SPECULATIVE_AT |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 442 | mrs x15, sctlr_el1 |
Manish V Badarkhe | 2b0ee97 | 2020-07-28 07:22:30 +0100 | [diff] [blame] | 443 | mrs x16, tcr_el1 |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 444 | stp x15, x16, [x0, #CTX_SCTLR_EL1] |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 445 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 446 | |
| 447 | mrs x17, cpacr_el1 |
| 448 | mrs x9, csselr_el1 |
| 449 | stp x17, x9, [x0, #CTX_CPACR_EL1] |
| 450 | |
| 451 | mrs x10, sp_el1 |
| 452 | mrs x11, esr_el1 |
| 453 | stp x10, x11, [x0, #CTX_SP_EL1] |
| 454 | |
| 455 | mrs x12, ttbr0_el1 |
| 456 | mrs x13, ttbr1_el1 |
| 457 | stp x12, x13, [x0, #CTX_TTBR0_EL1] |
| 458 | |
| 459 | mrs x14, mair_el1 |
| 460 | mrs x15, amair_el1 |
| 461 | stp x14, x15, [x0, #CTX_MAIR_EL1] |
| 462 | |
Manish V Badarkhe | 2b0ee97 | 2020-07-28 07:22:30 +0100 | [diff] [blame] | 463 | mrs x16, actlr_el1 |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 464 | mrs x17, tpidr_el1 |
Manish V Badarkhe | 2b0ee97 | 2020-07-28 07:22:30 +0100 | [diff] [blame] | 465 | stp x16, x17, [x0, #CTX_ACTLR_EL1] |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 466 | |
| 467 | mrs x9, tpidr_el0 |
| 468 | mrs x10, tpidrro_el0 |
| 469 | stp x9, x10, [x0, #CTX_TPIDR_EL0] |
| 470 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 471 | mrs x13, par_el1 |
| 472 | mrs x14, far_el1 |
| 473 | stp x13, x14, [x0, #CTX_PAR_EL1] |
| 474 | |
| 475 | mrs x15, afsr0_el1 |
| 476 | mrs x16, afsr1_el1 |
| 477 | stp x15, x16, [x0, #CTX_AFSR0_EL1] |
| 478 | |
| 479 | mrs x17, contextidr_el1 |
| 480 | mrs x9, vbar_el1 |
| 481 | stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] |
| 482 | |
Soby Mathew | d75d2ba | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 483 | /* Save AArch32 system registers if the build has instructed so */ |
| 484 | #if CTX_INCLUDE_AARCH32_REGS |
| 485 | mrs x11, spsr_abt |
| 486 | mrs x12, spsr_und |
| 487 | stp x11, x12, [x0, #CTX_SPSR_ABT] |
| 488 | |
| 489 | mrs x13, spsr_irq |
| 490 | mrs x14, spsr_fiq |
| 491 | stp x13, x14, [x0, #CTX_SPSR_IRQ] |
| 492 | |
| 493 | mrs x15, dacr32_el2 |
| 494 | mrs x16, ifsr32_el2 |
| 495 | stp x15, x16, [x0, #CTX_DACR32_EL2] |
Soby Mathew | d75d2ba | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 496 | #endif |
| 497 | |
Jeenu Viswambharan | d1b6015 | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 498 | /* Save NS timer registers if the build has instructed so */ |
| 499 | #if NS_TIMER_SWITCH |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 500 | mrs x10, cntp_ctl_el0 |
| 501 | mrs x11, cntp_cval_el0 |
| 502 | stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] |
| 503 | |
| 504 | mrs x12, cntv_ctl_el0 |
| 505 | mrs x13, cntv_cval_el0 |
| 506 | stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] |
| 507 | |
| 508 | mrs x14, cntkctl_el1 |
Jeenu Viswambharan | d1b6015 | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 509 | str x14, [x0, #CTX_CNTKCTL_EL1] |
| 510 | #endif |
| 511 | |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 512 | /* Save MTE system registers if the build has instructed so */ |
| 513 | #if CTX_INCLUDE_MTE_REGS |
| 514 | mrs x15, TFSRE0_EL1 |
| 515 | mrs x16, TFSR_EL1 |
| 516 | stp x15, x16, [x0, #CTX_TFSRE0_EL1] |
| 517 | |
| 518 | mrs x9, RGSR_EL1 |
| 519 | mrs x10, GCR_EL1 |
| 520 | stp x9, x10, [x0, #CTX_RGSR_EL1] |
| 521 | #endif |
| 522 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 523 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 524 | endfunc el1_sysregs_context_save |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 525 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 526 | /* ------------------------------------------------------------------ |
| 527 | * The following function strictly follows the AArch64 PCS to use |
| 528 | * x9-x17 (temporary caller-saved registers) to restore EL1 system |
| 529 | * register context. It assumes that 'x0' is pointing to a |
| 530 | * 'el1_sys_regs' structure from where the register context will be |
| 531 | * restored |
| 532 | * ------------------------------------------------------------------ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 533 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 534 | func el1_sysregs_context_restore |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 535 | |
| 536 | ldp x9, x10, [x0, #CTX_SPSR_EL1] |
| 537 | msr spsr_el1, x9 |
| 538 | msr elr_el1, x10 |
| 539 | |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 540 | #if !ERRATA_SPECULATIVE_AT |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 541 | ldp x15, x16, [x0, #CTX_SCTLR_EL1] |
| 542 | msr sctlr_el1, x15 |
Manish V Badarkhe | 2b0ee97 | 2020-07-28 07:22:30 +0100 | [diff] [blame] | 543 | msr tcr_el1, x16 |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 544 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 545 | |
| 546 | ldp x17, x9, [x0, #CTX_CPACR_EL1] |
| 547 | msr cpacr_el1, x17 |
| 548 | msr csselr_el1, x9 |
| 549 | |
| 550 | ldp x10, x11, [x0, #CTX_SP_EL1] |
| 551 | msr sp_el1, x10 |
| 552 | msr esr_el1, x11 |
| 553 | |
| 554 | ldp x12, x13, [x0, #CTX_TTBR0_EL1] |
| 555 | msr ttbr0_el1, x12 |
| 556 | msr ttbr1_el1, x13 |
| 557 | |
| 558 | ldp x14, x15, [x0, #CTX_MAIR_EL1] |
| 559 | msr mair_el1, x14 |
| 560 | msr amair_el1, x15 |
| 561 | |
Manish V Badarkhe | 2b0ee97 | 2020-07-28 07:22:30 +0100 | [diff] [blame] | 562 | ldp x16, x17, [x0, #CTX_ACTLR_EL1] |
| 563 | msr actlr_el1, x16 |
Manish V Badarkhe | d73c1ba | 2020-07-28 07:12:56 +0100 | [diff] [blame] | 564 | msr tpidr_el1, x17 |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 565 | |
| 566 | ldp x9, x10, [x0, #CTX_TPIDR_EL0] |
| 567 | msr tpidr_el0, x9 |
| 568 | msr tpidrro_el0, x10 |
| 569 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 570 | ldp x13, x14, [x0, #CTX_PAR_EL1] |
| 571 | msr par_el1, x13 |
| 572 | msr far_el1, x14 |
| 573 | |
| 574 | ldp x15, x16, [x0, #CTX_AFSR0_EL1] |
| 575 | msr afsr0_el1, x15 |
| 576 | msr afsr1_el1, x16 |
| 577 | |
| 578 | ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] |
| 579 | msr contextidr_el1, x17 |
| 580 | msr vbar_el1, x9 |
| 581 | |
Soby Mathew | d75d2ba | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 582 | /* Restore AArch32 system registers if the build has instructed so */ |
| 583 | #if CTX_INCLUDE_AARCH32_REGS |
| 584 | ldp x11, x12, [x0, #CTX_SPSR_ABT] |
| 585 | msr spsr_abt, x11 |
| 586 | msr spsr_und, x12 |
| 587 | |
| 588 | ldp x13, x14, [x0, #CTX_SPSR_IRQ] |
| 589 | msr spsr_irq, x13 |
| 590 | msr spsr_fiq, x14 |
| 591 | |
| 592 | ldp x15, x16, [x0, #CTX_DACR32_EL2] |
| 593 | msr dacr32_el2, x15 |
| 594 | msr ifsr32_el2, x16 |
Soby Mathew | d75d2ba | 2016-05-17 14:01:32 +0100 | [diff] [blame] | 595 | #endif |
Jeenu Viswambharan | d1b6015 | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 596 | /* Restore NS timer registers if the build has instructed so */ |
| 597 | #if NS_TIMER_SWITCH |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 598 | ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] |
| 599 | msr cntp_ctl_el0, x10 |
| 600 | msr cntp_cval_el0, x11 |
| 601 | |
| 602 | ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] |
| 603 | msr cntv_ctl_el0, x12 |
| 604 | msr cntv_cval_el0, x13 |
| 605 | |
Jeenu Viswambharan | d1b6015 | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 606 | ldr x14, [x0, #CTX_CNTKCTL_EL1] |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 607 | msr cntkctl_el1, x14 |
Jeenu Viswambharan | d1b6015 | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 608 | #endif |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 609 | /* Restore MTE system registers if the build has instructed so */ |
| 610 | #if CTX_INCLUDE_MTE_REGS |
| 611 | ldp x11, x12, [x0, #CTX_TFSRE0_EL1] |
| 612 | msr TFSRE0_EL1, x11 |
| 613 | msr TFSR_EL1, x12 |
| 614 | |
| 615 | ldp x13, x14, [x0, #CTX_RGSR_EL1] |
| 616 | msr RGSR_EL1, x13 |
| 617 | msr GCR_EL1, x14 |
| 618 | #endif |
Jeenu Viswambharan | d1b6015 | 2014-05-12 15:28:47 +0100 | [diff] [blame] | 619 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 620 | /* No explict ISB required here as ERET covers it */ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 621 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 622 | endfunc el1_sysregs_context_restore |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 623 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 624 | /* ------------------------------------------------------------------ |
| 625 | * The following function follows the aapcs_64 strictly to use |
| 626 | * x9-x17 (temporary caller-saved registers according to AArch64 PCS) |
| 627 | * to save floating point register context. It assumes that 'x0' is |
| 628 | * pointing to a 'fp_regs' structure where the register context will |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 629 | * be saved. |
| 630 | * |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 631 | * Access to VFP registers will trap if CPTR_EL3.TFP is set. |
| 632 | * However currently we don't use VFP registers nor set traps in |
| 633 | * Trusted Firmware, and assume it's cleared. |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 634 | * |
| 635 | * TODO: Revisit when VFP is used in secure world |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 636 | * ------------------------------------------------------------------ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 637 | */ |
Juan Castillo | 258e94f | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 638 | #if CTX_INCLUDE_FPREGS |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 639 | func fpregs_context_save |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 640 | stp q0, q1, [x0, #CTX_FP_Q0] |
| 641 | stp q2, q3, [x0, #CTX_FP_Q2] |
| 642 | stp q4, q5, [x0, #CTX_FP_Q4] |
| 643 | stp q6, q7, [x0, #CTX_FP_Q6] |
| 644 | stp q8, q9, [x0, #CTX_FP_Q8] |
| 645 | stp q10, q11, [x0, #CTX_FP_Q10] |
| 646 | stp q12, q13, [x0, #CTX_FP_Q12] |
| 647 | stp q14, q15, [x0, #CTX_FP_Q14] |
| 648 | stp q16, q17, [x0, #CTX_FP_Q16] |
| 649 | stp q18, q19, [x0, #CTX_FP_Q18] |
| 650 | stp q20, q21, [x0, #CTX_FP_Q20] |
| 651 | stp q22, q23, [x0, #CTX_FP_Q22] |
| 652 | stp q24, q25, [x0, #CTX_FP_Q24] |
| 653 | stp q26, q27, [x0, #CTX_FP_Q26] |
| 654 | stp q28, q29, [x0, #CTX_FP_Q28] |
| 655 | stp q30, q31, [x0, #CTX_FP_Q30] |
| 656 | |
| 657 | mrs x9, fpsr |
| 658 | str x9, [x0, #CTX_FP_FPSR] |
| 659 | |
| 660 | mrs x10, fpcr |
| 661 | str x10, [x0, #CTX_FP_FPCR] |
| 662 | |
David Cunado | d1a1fd4 | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 663 | #if CTX_INCLUDE_AARCH32_REGS |
| 664 | mrs x11, fpexc32_el2 |
| 665 | str x11, [x0, #CTX_FP_FPEXC32_EL2] |
| 666 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 667 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 668 | endfunc fpregs_context_save |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 669 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 670 | /* ------------------------------------------------------------------ |
| 671 | * The following function follows the aapcs_64 strictly to use x9-x17 |
| 672 | * (temporary caller-saved registers according to AArch64 PCS) to |
| 673 | * restore floating point register context. It assumes that 'x0' is |
| 674 | * pointing to a 'fp_regs' structure from where the register context |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 675 | * will be restored. |
| 676 | * |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 677 | * Access to VFP registers will trap if CPTR_EL3.TFP is set. |
| 678 | * However currently we don't use VFP registers nor set traps in |
| 679 | * Trusted Firmware, and assume it's cleared. |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 680 | * |
| 681 | * TODO: Revisit when VFP is used in secure world |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 682 | * ------------------------------------------------------------------ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 683 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 684 | func fpregs_context_restore |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 685 | ldp q0, q1, [x0, #CTX_FP_Q0] |
| 686 | ldp q2, q3, [x0, #CTX_FP_Q2] |
| 687 | ldp q4, q5, [x0, #CTX_FP_Q4] |
| 688 | ldp q6, q7, [x0, #CTX_FP_Q6] |
| 689 | ldp q8, q9, [x0, #CTX_FP_Q8] |
| 690 | ldp q10, q11, [x0, #CTX_FP_Q10] |
| 691 | ldp q12, q13, [x0, #CTX_FP_Q12] |
| 692 | ldp q14, q15, [x0, #CTX_FP_Q14] |
| 693 | ldp q16, q17, [x0, #CTX_FP_Q16] |
| 694 | ldp q18, q19, [x0, #CTX_FP_Q18] |
| 695 | ldp q20, q21, [x0, #CTX_FP_Q20] |
| 696 | ldp q22, q23, [x0, #CTX_FP_Q22] |
| 697 | ldp q24, q25, [x0, #CTX_FP_Q24] |
| 698 | ldp q26, q27, [x0, #CTX_FP_Q26] |
| 699 | ldp q28, q29, [x0, #CTX_FP_Q28] |
| 700 | ldp q30, q31, [x0, #CTX_FP_Q30] |
| 701 | |
| 702 | ldr x9, [x0, #CTX_FP_FPSR] |
| 703 | msr fpsr, x9 |
| 704 | |
Soby Mathew | e77e116 | 2015-12-03 09:42:50 +0000 | [diff] [blame] | 705 | ldr x10, [x0, #CTX_FP_FPCR] |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 706 | msr fpcr, x10 |
| 707 | |
David Cunado | d1a1fd4 | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 708 | #if CTX_INCLUDE_AARCH32_REGS |
| 709 | ldr x11, [x0, #CTX_FP_FPEXC32_EL2] |
| 710 | msr fpexc32_el2, x11 |
| 711 | #endif |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 712 | /* |
| 713 | * No explict ISB required here as ERET to |
Sandrine Bailleux | f4119ec | 2015-12-17 13:58:58 +0000 | [diff] [blame] | 714 | * switch to secure EL1 or non-secure world |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 715 | * covers it |
| 716 | */ |
| 717 | |
| 718 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 719 | endfunc fpregs_context_restore |
Juan Castillo | 258e94f | 2014-06-25 17:26:36 +0100 | [diff] [blame] | 720 | #endif /* CTX_INCLUDE_FPREGS */ |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 721 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 722 | /* ------------------------------------------------------------------ |
| 723 | * The following function is used to save and restore all the general |
| 724 | * purpose and ARMv8.3-PAuth (if enabled) registers. |
| 725 | * It also checks if Secure Cycle Counter is not disabled in MDCR_EL3 |
| 726 | * when ARMv8.5-PMU is implemented, and if called from Non-secure |
| 727 | * state saves PMCR_EL0 and disables Cycle Counter. |
| 728 | * |
| 729 | * Ideally we would only save and restore the callee saved registers |
| 730 | * when a world switch occurs but that type of implementation is more |
| 731 | * complex. So currently we will always save and restore these |
| 732 | * registers on entry and exit of EL3. |
| 733 | * These are not macros to ensure their invocation fits within the 32 |
| 734 | * instructions per exception vector. |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 735 | * clobbers: x18 |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 736 | * ------------------------------------------------------------------ |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 737 | */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 738 | func save_gp_pmcr_pauth_regs |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 739 | stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 740 | stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] |
| 741 | stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 742 | stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] |
| 743 | stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] |
| 744 | stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] |
| 745 | stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] |
| 746 | stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] |
| 747 | stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] |
| 748 | stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] |
| 749 | stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] |
| 750 | stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] |
| 751 | stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] |
| 752 | stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] |
| 753 | stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
| 754 | mrs x18, sp_el0 |
| 755 | str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 756 | |
| 757 | /* ---------------------------------------------------------- |
| 758 | * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, |
| 759 | * meaning that ARMv8-PMU is not implemented and PMCR_EL0 |
| 760 | * should be saved in non-secure context. |
| 761 | * ---------------------------------------------------------- |
| 762 | */ |
| 763 | mrs x9, mdcr_el3 |
| 764 | tst x9, #MDCR_SCCD_BIT |
| 765 | bne 1f |
| 766 | |
| 767 | /* Secure Cycle Counter is not disabled */ |
| 768 | mrs x9, pmcr_el0 |
| 769 | |
| 770 | /* Check caller's security state */ |
| 771 | mrs x10, scr_el3 |
| 772 | tst x10, #SCR_NS_BIT |
| 773 | beq 2f |
| 774 | |
| 775 | /* Save PMCR_EL0 if called from Non-secure state */ |
| 776 | str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] |
| 777 | |
| 778 | /* Disable cycle counter when event counting is prohibited */ |
| 779 | 2: orr x9, x9, #PMCR_EL0_DP_BIT |
| 780 | msr pmcr_el0, x9 |
| 781 | isb |
| 782 | 1: |
| 783 | #if CTX_INCLUDE_PAUTH_REGS |
| 784 | /* ---------------------------------------------------------- |
| 785 | * Save the ARMv8.3-PAuth keys as they are not banked |
| 786 | * by exception level |
| 787 | * ---------------------------------------------------------- |
| 788 | */ |
| 789 | add x19, sp, #CTX_PAUTH_REGS_OFFSET |
| 790 | |
| 791 | mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ |
| 792 | mrs x21, APIAKeyHi_EL1 |
| 793 | mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ |
| 794 | mrs x23, APIBKeyHi_EL1 |
| 795 | mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ |
| 796 | mrs x25, APDAKeyHi_EL1 |
| 797 | mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ |
| 798 | mrs x27, APDBKeyHi_EL1 |
| 799 | mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ |
| 800 | mrs x29, APGAKeyHi_EL1 |
| 801 | |
| 802 | stp x20, x21, [x19, #CTX_PACIAKEY_LO] |
| 803 | stp x22, x23, [x19, #CTX_PACIBKEY_LO] |
| 804 | stp x24, x25, [x19, #CTX_PACDAKEY_LO] |
| 805 | stp x26, x27, [x19, #CTX_PACDBKEY_LO] |
| 806 | stp x28, x29, [x19, #CTX_PACGAKEY_LO] |
| 807 | #endif /* CTX_INCLUDE_PAUTH_REGS */ |
| 808 | |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 809 | ret |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 810 | endfunc save_gp_pmcr_pauth_regs |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 811 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 812 | /* ------------------------------------------------------------------ |
| 813 | * This function restores ARMv8.3-PAuth (if enabled) and all general |
| 814 | * purpose registers except x30 from the CPU context. |
| 815 | * x30 register must be explicitly restored by the caller. |
| 816 | * ------------------------------------------------------------------ |
Jeenu Viswambharan | 23d05a8 | 2017-11-29 16:59:34 +0000 | [diff] [blame] | 817 | */ |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 818 | func restore_gp_pmcr_pauth_regs |
| 819 | #if CTX_INCLUDE_PAUTH_REGS |
| 820 | /* Restore the ARMv8.3 PAuth keys */ |
| 821 | add x10, sp, #CTX_PAUTH_REGS_OFFSET |
| 822 | |
| 823 | ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ |
| 824 | ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ |
| 825 | ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ |
| 826 | ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ |
| 827 | ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ |
| 828 | |
| 829 | msr APIAKeyLo_EL1, x0 |
| 830 | msr APIAKeyHi_EL1, x1 |
| 831 | msr APIBKeyLo_EL1, x2 |
| 832 | msr APIBKeyHi_EL1, x3 |
| 833 | msr APDAKeyLo_EL1, x4 |
| 834 | msr APDAKeyHi_EL1, x5 |
| 835 | msr APDBKeyLo_EL1, x6 |
| 836 | msr APDBKeyHi_EL1, x7 |
| 837 | msr APGAKeyLo_EL1, x8 |
| 838 | msr APGAKeyHi_EL1, x9 |
| 839 | #endif /* CTX_INCLUDE_PAUTH_REGS */ |
| 840 | |
| 841 | /* ---------------------------------------------------------- |
| 842 | * Restore PMCR_EL0 when returning to Non-secure state if |
| 843 | * Secure Cycle Counter is not disabled in MDCR_EL3 when |
| 844 | * ARMv8.5-PMU is implemented. |
| 845 | * ---------------------------------------------------------- |
| 846 | */ |
| 847 | mrs x0, scr_el3 |
| 848 | tst x0, #SCR_NS_BIT |
| 849 | beq 2f |
| 850 | |
| 851 | /* ---------------------------------------------------------- |
| 852 | * Back to Non-secure state. |
| 853 | * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, |
| 854 | * meaning that ARMv8-PMU is not implemented and PMCR_EL0 |
| 855 | * should be restored from non-secure context. |
| 856 | * ---------------------------------------------------------- |
| 857 | */ |
| 858 | mrs x0, mdcr_el3 |
| 859 | tst x0, #MDCR_SCCD_BIT |
| 860 | bne 2f |
| 861 | ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] |
| 862 | msr pmcr_el0, x0 |
| 863 | 2: |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 864 | ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 865 | ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 866 | ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 867 | ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] |
| 868 | ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] |
| 869 | ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] |
| 870 | ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] |
| 871 | ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] |
Jeenu Viswambharan | 23d05a8 | 2017-11-29 16:59:34 +0000 | [diff] [blame] | 872 | ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 873 | ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] |
| 874 | ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] |
| 875 | ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] |
| 876 | ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] |
| 877 | ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] |
Jeenu Viswambharan | 23d05a8 | 2017-11-29 16:59:34 +0000 | [diff] [blame] | 878 | ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] |
| 879 | msr sp_el0, x28 |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 880 | ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] |
Jeenu Viswambharan | 23d05a8 | 2017-11-29 16:59:34 +0000 | [diff] [blame] | 881 | ret |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 882 | endfunc restore_gp_pmcr_pauth_regs |
Jeenu Viswambharan | 23d05a8 | 2017-11-29 16:59:34 +0000 | [diff] [blame] | 883 | |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 884 | /* |
| 885 | * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1 |
| 886 | * registers and update EL1 registers to disable stage1 and stage2 |
| 887 | * page table walk |
| 888 | */ |
| 889 | func save_and_update_ptw_el1_sys_regs |
| 890 | /* ---------------------------------------------------------- |
| 891 | * Save only sctlr_el1 and tcr_el1 registers |
| 892 | * ---------------------------------------------------------- |
| 893 | */ |
| 894 | mrs x29, sctlr_el1 |
| 895 | str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1)] |
| 896 | mrs x29, tcr_el1 |
| 897 | str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_TCR_EL1)] |
| 898 | |
| 899 | /* ------------------------------------------------------------ |
| 900 | * Must follow below order in order to disable page table |
| 901 | * walk for lower ELs (EL1 and EL0). First step ensures that |
| 902 | * page table walk is disabled for stage1 and second step |
| 903 | * ensures that page table walker should use TCR_EL1.EPDx |
| 904 | * bits to perform address translation. ISB ensures that CPU |
| 905 | * does these 2 steps in order. |
| 906 | * |
| 907 | * 1. Update TCR_EL1.EPDx bits to disable page table walk by |
| 908 | * stage1. |
| 909 | * 2. Enable MMU bit to avoid identity mapping via stage2 |
| 910 | * and force TCR_EL1.EPDx to be used by the page table |
| 911 | * walker. |
| 912 | * ------------------------------------------------------------ |
| 913 | */ |
| 914 | orr x29, x29, #(TCR_EPD0_BIT) |
| 915 | orr x29, x29, #(TCR_EPD1_BIT) |
| 916 | msr tcr_el1, x29 |
| 917 | isb |
| 918 | mrs x29, sctlr_el1 |
| 919 | orr x29, x29, #SCTLR_M_BIT |
| 920 | msr sctlr_el1, x29 |
| 921 | isb |
| 922 | |
| 923 | ret |
| 924 | endfunc save_and_update_ptw_el1_sys_regs |
| 925 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 926 | /* ------------------------------------------------------------------ |
| 927 | * This routine assumes that the SP_EL3 is pointing to a valid |
| 928 | * context structure from where the gp regs and other special |
| 929 | * registers can be retrieved. |
| 930 | * ------------------------------------------------------------------ |
Antonio Nino Diaz | 13adfb1 | 2019-01-30 20:41:31 +0000 | [diff] [blame] | 931 | */ |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 932 | func el3_exit |
Jan Dabros | fa01598 | 2019-12-02 13:30:03 +0100 | [diff] [blame] | 933 | #if ENABLE_ASSERTIONS |
| 934 | /* el3_exit assumes SP_EL0 on entry */ |
| 935 | mrs x17, spsel |
| 936 | cmp x17, #MODE_SP_EL0 |
| 937 | ASM_ASSERT(eq) |
| 938 | #endif |
| 939 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 940 | /* ---------------------------------------------------------- |
| 941 | * Save the current SP_EL0 i.e. the EL3 runtime stack which |
| 942 | * will be used for handling the next SMC. |
| 943 | * Then switch to SP_EL3. |
| 944 | * ---------------------------------------------------------- |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 945 | */ |
| 946 | mov x17, sp |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 947 | msr spsel, #MODE_SP_ELX |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 948 | str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 949 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 950 | /* ---------------------------------------------------------- |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 951 | * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 952 | * ---------------------------------------------------------- |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 953 | */ |
| 954 | ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] |
| 955 | ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 956 | msr scr_el3, x18 |
| 957 | msr spsr_el3, x16 |
| 958 | msr elr_el3, x17 |
| 959 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 960 | #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 961 | /* ---------------------------------------------------------- |
| 962 | * Restore mitigation state as it was on entry to EL3 |
| 963 | * ---------------------------------------------------------- |
| 964 | */ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 965 | ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 966 | cbz x17, 1f |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 967 | blr x17 |
Antonio Nino Diaz | 13adfb1 | 2019-01-30 20:41:31 +0000 | [diff] [blame] | 968 | 1: |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 969 | #endif |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 970 | restore_ptw_el1_sys_regs |
| 971 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 972 | /* ---------------------------------------------------------- |
| 973 | * Restore general purpose (including x30), PMCR_EL0 and |
| 974 | * ARMv8.3-PAuth registers. |
| 975 | * Exit EL3 via ERET to a lower exception level. |
| 976 | * ---------------------------------------------------------- |
| 977 | */ |
| 978 | bl restore_gp_pmcr_pauth_regs |
| 979 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 980 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 981 | #if IMAGE_BL31 && RAS_EXTENSION |
| 982 | /* ---------------------------------------------------------- |
| 983 | * Issue Error Synchronization Barrier to synchronize SErrors |
| 984 | * before exiting EL3. We're running with EAs unmasked, so |
| 985 | * any synchronized errors would be taken immediately; |
| 986 | * therefore no need to inspect DISR_EL1 register. |
| 987 | * ---------------------------------------------------------- |
| 988 | */ |
| 989 | esb |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 990 | #endif |
Anthony Steinhauser | 0f7e601 | 2020-01-07 15:44:06 -0800 | [diff] [blame] | 991 | exception_return |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 992 | |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 993 | endfunc el3_exit |