blob: 68ad5f632e4bdeb25d906208075686bf40cd8d58 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew981487a2015-07-13 14:10:57 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000034#include <debug.h>
35#include <platform.h>
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000036#include <runtime_svc.h>
Soby Mathew6cdddaf2015-01-07 11:10:22 +000037#include <std_svc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010038#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010039#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
43 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010044int psci_cpu_on(u_register_t target_cpu,
45 uintptr_t entrypoint,
46 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
48{
49 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000050 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010051
52 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010053 rc = psci_validate_mpidr(target_cpu);
54 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010055 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010056
Soby Mathewf1f97a12015-07-15 12:13:26 +010057 /* Validate the entry point and get the entry_point_info */
58 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000059 if (rc != PSCI_E_SUCCESS)
60 return rc;
61
Soby Mathew8595b872015-01-06 15:36:38 +000062 /*
Soby Mathew981487a2015-07-13 14:10:57 +010063 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000064 * levels need to be turned on
65 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010066 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010067}
68
69unsigned int psci_version(void)
70{
71 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
72}
73
74int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010075 uintptr_t entrypoint,
76 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010077{
78 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010079 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000080 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010081 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
82 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010083
Soby Mathew981487a2015-07-13 14:10:57 +010084 /* Validate the power_state parameter */
85 rc = psci_validate_power_state(power_state, &state_info);
86 if (rc != PSCI_E_SUCCESS) {
87 assert(rc == PSCI_E_INVALID_PARAMS);
88 return rc;
89 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010090
Soby Mathew981487a2015-07-13 14:10:57 +010091 /*
92 * Get the value of the state type bit from the power state parameter.
93 */
94 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010095
Soby Mathew981487a2015-07-13 14:10:57 +010096 /* Sanity check the requested suspend levels */
97 assert (psci_validate_suspend_req(&state_info, is_power_down_state)
98 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010099
Soby Mathew981487a2015-07-13 14:10:57 +0100100 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
101
102 /* Fast path for CPU standby.*/
103 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
104 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +0100105 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +0100106
Soby Mathew981487a2015-07-13 14:10:57 +0100107 /*
108 * Set the state of the CPU power domain to the platform
109 * specific retention state and enter the standby state.
110 */
111 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
112 psci_set_cpu_local_state(cpu_pd_state);
113 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100114
Soby Mathew981487a2015-07-13 14:10:57 +0100115 /* Upon exit from standby, set the state back to RUN. */
116 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100117
Soby Mathew74e52a72014-10-02 16:56:51 +0100118 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000119 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120
Achin Gupta42c52802014-05-09 19:32:25 +0100121 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100122 * If a power down state has been requested, we need to verify entry
123 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000124 */
Soby Mathew981487a2015-07-13 14:10:57 +0100125 if (is_power_down_state) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100126 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100127 if (rc != PSCI_E_SUCCESS)
128 return rc;
129 }
Soby Mathewf5121572014-09-30 11:19:51 +0100130
Soby Mathew8595b872015-01-06 15:36:38 +0000131 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100132 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100133 * enter the final wfi which will power down this CPU. This function
134 * might return if the power down was abandoned for any reason, e.g.
135 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100136 */
Soby Mathew981487a2015-07-13 14:10:57 +0100137 psci_cpu_suspend_start(&ep,
138 target_pwrlvl,
139 &state_info,
140 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100141
Soby Mathew74e52a72014-10-02 16:56:51 +0100142 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100143}
144
Soby Mathew011ca182015-07-29 17:05:03 +0100145
146int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000147{
148 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100149 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000150 entry_point_info_t ep;
151
Soby Mathew96168382014-12-17 14:47:57 +0000152 /* Check if the current CPU is the last ON CPU in the system */
153 if (!psci_is_last_on_cpu())
154 return PSCI_E_DENIED;
155
Soby Mathewf1f97a12015-07-15 12:13:26 +0100156 /* Validate the entry point and get the entry_point_info */
157 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000158 if (rc != PSCI_E_SUCCESS)
159 return rc;
160
Soby Mathew981487a2015-07-13 14:10:57 +0100161 /* Query the psci_power_state for system suspend */
162 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000163
Soby Mathew981487a2015-07-13 14:10:57 +0100164 /* Ensure that the psci_power_state makes sense */
165 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
166 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
167 == PSCI_E_SUCCESS);
168 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000169
170 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100171 * Do what is needed to enter the system suspend state. This function
172 * might return if the power down was abandoned for any reason, e.g.
173 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000174 */
Soby Mathew981487a2015-07-13 14:10:57 +0100175 psci_cpu_suspend_start(&ep,
176 PLAT_MAX_PWR_LVL,
177 &state_info,
178 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000179
Soby Mathew96168382014-12-17 14:47:57 +0000180 return PSCI_E_SUCCESS;
181}
182
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183int psci_cpu_off(void)
184{
185 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100186 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100189 * Do what is needed to power off this CPU and possible higher power
190 * levels if it able to do so. Upon success, enter the final wfi
191 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192 */
Soby Mathew981487a2015-07-13 14:10:57 +0100193 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194
Achin Gupta3140a9e2013-12-02 16:23:12 +0000195 /*
196 * The only error cpu_off can return is E_DENIED. So check if that's
197 * indeed the case.
198 */
Achin Gupta42c52802014-05-09 19:32:25 +0100199 assert (rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
201 return rc;
202}
203
Soby Mathew011ca182015-07-29 17:05:03 +0100204int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205 unsigned int lowest_affinity_level)
206{
Soby Mathew981487a2015-07-13 14:10:57 +0100207 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208
Soby Mathew981487a2015-07-13 14:10:57 +0100209 /* We dont support level higher than PSCI_CPU_PWR_LVL */
210 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
211 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212
Soby Mathew981487a2015-07-13 14:10:57 +0100213 /* Calculate the cpu index of the target */
214 target_idx = plat_core_pos_by_mpidr(target_affinity);
215 if (target_idx == -1)
216 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000217
Soby Mathew981487a2015-07-13 14:10:57 +0100218 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219}
220
Soby Mathew011ca182015-07-29 17:05:03 +0100221int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222{
Soby Mathew110fe362014-10-23 10:35:34 +0100223 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100224 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100225
226 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
227 if (rc != PSCI_TOS_UP_MIG_CAP)
228 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
229 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
230
231 /*
232 * Migrate should only be invoked on the CPU where
233 * the Secure OS is resident.
234 */
235 if (resident_cpu_mpidr != read_mpidr_el1())
236 return PSCI_E_NOT_PRESENT;
237
238 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100239 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100240 if (rc != PSCI_E_SUCCESS)
241 return PSCI_E_INVALID_PARAMS;
242
243 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
244
245 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
246 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
247
248 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249}
250
Soby Mathew110fe362014-10-23 10:35:34 +0100251int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252{
Soby Mathew011ca182015-07-29 17:05:03 +0100253 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100254
255 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256}
257
Soby Mathew110fe362014-10-23 10:35:34 +0100258long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259{
Soby Mathew011ca182015-07-29 17:05:03 +0100260 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100261 int rc;
262
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100264 * Return value of this depends upon what
265 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266 */
Soby Mathew110fe362014-10-23 10:35:34 +0100267 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
268 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
269 return PSCI_E_INVALID_PARAMS;
270
271 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272}
273
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000274int psci_features(unsigned int psci_fid)
275{
Soby Mathew011ca182015-07-29 17:05:03 +0100276 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000277
278 /* Check if it is a 64 bit function */
279 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
280 local_caps &= PSCI_CAP_64BIT_MASK;
281
282 /* Check for invalid fid */
283 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
284 && is_psci_fid(psci_fid)))
285 return PSCI_E_NOT_SUPPORTED;
286
287
288 /* Check if the psci fid is supported or not */
289 if (!(local_caps & define_psci_cap(psci_fid)))
290 return PSCI_E_NOT_SUPPORTED;
291
292 /* Format the feature flags */
293 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
294 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
295 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100296 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000297 */
Soby Mathew981487a2015-07-13 14:10:57 +0100298 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000299 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
300 }
301
302 /* Return 0 for all other fid's */
303 return PSCI_E_SUCCESS;
304}
305
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000306/*******************************************************************************
307 * PSCI top level handler for servicing SMCs.
308 ******************************************************************************/
309uint64_t psci_smc_handler(uint32_t smc_fid,
310 uint64_t x1,
311 uint64_t x2,
312 uint64_t x3,
313 uint64_t x4,
314 void *cookie,
315 void *handle,
316 uint64_t flags)
317{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100318 if (is_caller_secure(flags))
319 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000320
Soby Mathew61e615b2015-01-15 11:49:49 +0000321 /* Check the fid against the capabilities */
322 if (!(psci_caps & define_psci_cap(smc_fid)))
323 SMC_RET1(handle, SMC_UNK);
324
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100325 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
326 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000327
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100328 x1 = (uint32_t)x1;
329 x2 = (uint32_t)x2;
330 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000331
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100332 switch (smc_fid) {
333 case PSCI_VERSION:
334 SMC_RET1(handle, psci_version());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000335
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100336 case PSCI_CPU_OFF:
Achin Guptae1aa5162014-06-26 09:58:52 +0100337 SMC_RET1(handle, psci_cpu_off());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000338
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100339 case PSCI_CPU_SUSPEND_AARCH32:
Achin Guptae1aa5162014-06-26 09:58:52 +0100340 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000341
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100342 case PSCI_CPU_ON_AARCH32:
343 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000344
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100345 case PSCI_AFFINITY_INFO_AARCH32:
346 SMC_RET1(handle, psci_affinity_info(x1, x2));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000347
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100348 case PSCI_MIG_AARCH32:
349 SMC_RET1(handle, psci_migrate(x1));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000350
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100351 case PSCI_MIG_INFO_TYPE:
352 SMC_RET1(handle, psci_migrate_info_type());
353
354 case PSCI_MIG_INFO_UP_CPU_AARCH32:
355 SMC_RET1(handle, psci_migrate_info_up_cpu());
356
Soby Mathew96168382014-12-17 14:47:57 +0000357 case PSCI_SYSTEM_SUSPEND_AARCH32:
358 SMC_RET1(handle, psci_system_suspend(x1, x2));
359
Juan Castillo4dc4a472014-08-12 11:17:06 +0100360 case PSCI_SYSTEM_OFF:
361 psci_system_off();
362 /* We should never return from psci_system_off() */
363
364 case PSCI_SYSTEM_RESET:
365 psci_system_reset();
366 /* We should never return from psci_system_reset() */
367
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000368 case PSCI_FEATURES:
369 SMC_RET1(handle, psci_features(x1));
370
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100371 default:
372 break;
373 }
374 } else {
375 /* 64-bit PSCI function */
376
377 switch (smc_fid) {
378 case PSCI_CPU_SUSPEND_AARCH64:
Achin Guptae1aa5162014-06-26 09:58:52 +0100379 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100380
381 case PSCI_CPU_ON_AARCH64:
382 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
383
384 case PSCI_AFFINITY_INFO_AARCH64:
385 SMC_RET1(handle, psci_affinity_info(x1, x2));
386
387 case PSCI_MIG_AARCH64:
388 SMC_RET1(handle, psci_migrate(x1));
389
390 case PSCI_MIG_INFO_UP_CPU_AARCH64:
391 SMC_RET1(handle, psci_migrate_info_up_cpu());
392
Soby Mathew96168382014-12-17 14:47:57 +0000393 case PSCI_SYSTEM_SUSPEND_AARCH64:
394 SMC_RET1(handle, psci_system_suspend(x1, x2));
395
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100396 default:
397 break;
398 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000399 }
400
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100401 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
402 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000403}