Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 94cc0f850aa1ca5d47294005744811c899a91425 / . / plat / nvidia / tegra / include / t210 / tegra_def.h
blob: 14cdfd59dbdbe09610f66b9683b34bae91777c66 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]11
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]12/*******************************************************************************
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]13 * Power down state IDs
14 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]15#define PSTATE_ID_CORE_POWERDN U(7)
16#define PSTATE_ID_CLUSTER_IDLE U(16)
17#define PSTATE_ID_CLUSTER_POWERDN U(17)
18#define PSTATE_ID_SOC_POWERDN U(27)
Varun Wadekar81b13832015-07-03 16:31:28 +0530[diff] [blame]19
20/*******************************************************************************
21 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
22 * call as the `state-id` field in the 'power state' parameter.
23 ******************************************************************************/
24#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
25
26/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]27 * Platform power states (used by PSCI framework)
28 *
29 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
30 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
31 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]32#define PLAT_MAX_RET_STATE U(1)
33#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]34
35/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]36 * GIC memory map
37 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]38#define TEGRA_GICD_BASE U(0x50041000)
39#define TEGRA_GICC_BASE U(0x50042000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]40
41/*******************************************************************************
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]42 * Tegra Memory Select Switch Controller constants
43 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]44#define TEGRA_MSELECT_BASE U(0x50060000)
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]45
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]46#define MSELECT_CONFIG U(0x0)
47#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
48#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
49#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
50#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
51#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
Varun Wadekarbc787442015-07-27 13:00:50 +0530[diff] [blame]52#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
53 UNSUPPORTED_TX_ERR_MASTER1_BIT)
54#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
55 ENABLE_WRAP_INCR_MASTER1_BIT | \
56 ENABLE_WRAP_INCR_MASTER0_BIT)
57
58/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]59 * Tegra micro-seconds timer constants
60 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]61#define TEGRA_TMRUS_BASE U(0x60005010)
62#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]63
64/*******************************************************************************
65 * Tegra Clock and Reset Controller constants
66 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]67#define TEGRA_CAR_RESET_BASE U(0x60006000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]68#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
69#define GPU_RESET_BIT (U(1) << 24)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]70
71/*******************************************************************************
72 * Tegra Flow Controller constants
73 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]74#define TEGRA_FLOWCTRL_BASE U(0x60007000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]75
76/*******************************************************************************
77 * Tegra Secure Boot Controller constants
78 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]79#define TEGRA_SB_BASE U(0x6000C200)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]80
81/*******************************************************************************
82 * Tegra Exception Vectors constants
83 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]84#define TEGRA_EVP_BASE U(0x6000F000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]85
86/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]87 * Tegra Miscellaneous register constants
88 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]89#define TEGRA_MISC_BASE U(0x70000000)
90#define HARDWARE_REVISION_OFFSET U(0x804)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]91
92/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]93 * Tegra UART controller base addresses
94 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]95#define TEGRA_UARTA_BASE U(0x70006000)
96#define TEGRA_UARTB_BASE U(0x70006040)
97#define TEGRA_UARTC_BASE U(0x70006200)
98#define TEGRA_UARTD_BASE U(0x70006300)
99#define TEGRA_UARTE_BASE U(0x70006400)
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]100
101/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]102 * Tegra Power Mgmt Controller constants
103 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]104#define TEGRA_PMC_BASE U(0x7000E400)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]105
106/*******************************************************************************
107 * Tegra Memory Controller constants
108 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]109#define TEGRA_MC_BASE U(0x70019000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]110
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]111/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]112#define MC_SECURITY_CFG0_0 U(0x70)
113#define MC_SECURITY_CFG1_0 U(0x74)
114#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]115
116/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]117#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
118#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
119#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]120
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]121/*******************************************************************************
122 * Tegra TZRAM constants
123 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]124#define TEGRA_TZRAM_BASE U(0x7C010000)
125#define TEGRA_TZRAM_SIZE U(0x10000)
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]126
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]127#endif /* TEGRA_DEF_H */