| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 1 | /* |
| Jit Loon Lim | 5e76874 | 2023-05-17 12:26:11 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_SYSTEMMANAGER_H |
| 8 | #define SOCFPGA_SYSTEMMANAGER_H |
| 9 | |
| 10 | #include "socfpga_plat_def.h" |
| 11 | |
| 12 | /* System Manager Register Map */ |
| 13 | |
| 14 | #define SOCFPGA_SYSMGR_SDMMC 0x28 |
| 15 | |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 16 | /* Field Masking */ |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 17 | #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) |
| Tien Hock Loh | fcbc33d | 2020-05-11 01:11:39 -0700 | [diff] [blame] | 18 | #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 19 | |
| Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 20 | #define IDLE_DATA_LWSOC2FPGA BIT(4) |
| 21 | #define IDLE_DATA_SOC2FPGA BIT(0) |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 22 | #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) |
| 23 | |
| Jit Loon Lim | dd96d8f | 2022-08-19 13:40:17 +0200 | [diff] [blame] | 24 | #define SYSMGR_QSPI_REFCLK_MASK GENMASK(27, 0) |
| 25 | |
| Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 26 | #define SYSMGR_ECC_OCRAM_MASK BIT(1) |
| 27 | #define SYSMGR_ECC_DDR0_MASK BIT(16) |
| 28 | #define SYSMGR_ECC_DDR1_MASK BIT(17) |
| 29 | |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 30 | /* Macros */ |
| 31 | |
| 32 | #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ |
| 33 | + (SOCFPGA_SYSMGR_##_reg)) |
| 34 | |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 35 | #endif /* SOCFPGA_SYSTEMMANAGER_H */ |