Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
Varun Wadekar | 94701ff | 2016-05-23 11:47:34 -0700 | [diff] [blame] | 9 | #include <bl31.h> |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 10 | #include <bl_common.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 11 | #include <console.h> |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 12 | #include <context.h> |
| 13 | #include <context_mgmt.h> |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 14 | #include <cortex_a57.h> |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 15 | #include <debug.h> |
| 16 | #include <denver.h> |
Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 17 | #include <gic_common.h> |
| 18 | #include <gicv2.h> |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 19 | #include <interrupt_mgmt.h> |
Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 20 | #include <interrupt_props.h> |
Varun Wadekar | 47ddd00 | 2016-03-28 16:00:02 -0700 | [diff] [blame] | 21 | #include <mce.h> |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 22 | #include <platform.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 23 | #include <tegra_def.h> |
Varun Wadekar | 5887c10 | 2016-07-19 11:29:40 -0700 | [diff] [blame] | 24 | #include <tegra_platform.h> |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 25 | #include <tegra_private.h> |
Andreas Färber | 92cea4a | 2018-02-17 06:02:32 +0100 | [diff] [blame] | 26 | #include <xlat_tables_v2.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 27 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 28 | DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 29 | extern uint64_t tegra_enable_l2_ecc_parity_prot; |
| 30 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 31 | /******************************************************************************* |
Varun Wadekar | 43dad67 | 2017-01-31 14:53:37 -0800 | [diff] [blame] | 32 | * Tegra186 CPU numbers in cluster #0 |
| 33 | ******************************************************************************* |
| 34 | */ |
| 35 | #define TEGRA186_CLUSTER0_CORE2 2 |
| 36 | #define TEGRA186_CLUSTER0_CORE3 3 |
| 37 | |
| 38 | /******************************************************************************* |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 39 | * The Tegra power domain tree has a single system level power domain i.e. a |
| 40 | * single root node. The first entry in the power domain descriptor specifies |
| 41 | * the number of power domains at the highest power level. |
| 42 | ******************************************************************************* |
| 43 | */ |
| 44 | const unsigned char tegra_power_domain_tree_desc[] = { |
| 45 | /* No of root nodes */ |
| 46 | 1, |
| 47 | /* No of clusters */ |
| 48 | PLATFORM_CLUSTER_COUNT, |
| 49 | /* No of CPU cores - cluster0 */ |
| 50 | PLATFORM_MAX_CPUS_PER_CLUSTER, |
| 51 | /* No of CPU cores - cluster1 */ |
| 52 | PLATFORM_MAX_CPUS_PER_CLUSTER |
| 53 | }; |
| 54 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 55 | /* |
| 56 | * Table of regions to map using the MMU. |
| 57 | */ |
| 58 | static const mmap_region_t tegra_mmap[] = { |
| 59 | MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ |
| 60 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 61 | MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ |
| 62 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 63 | MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ |
| 64 | MT_DEVICE | MT_RW | MT_SECURE), |
| 65 | MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ |
| 66 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | 9db0ad1 | 2016-07-12 10:04:28 -0700 | [diff] [blame] | 67 | MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ |
| 68 | MT_DEVICE | MT_RW | MT_SECURE), |
| 69 | MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ |
| 70 | MT_DEVICE | MT_RW | MT_SECURE), |
| 71 | MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 72 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 73 | MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ |
| 74 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 75 | MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ |
| 76 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 77 | MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ |
| 78 | MT_DEVICE | MT_RW | MT_SECURE), |
| 79 | MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ |
| 80 | MT_DEVICE | MT_RW | MT_SECURE), |
| 81 | MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ |
| 82 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 83 | MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ |
| 84 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 85 | MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ |
| 86 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 87 | MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ |
| 88 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 89 | MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ |
| 90 | MT_DEVICE | MT_RW | MT_SECURE), |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 91 | MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ |
| 92 | MT_DEVICE | MT_RW | MT_SECURE), |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 93 | MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 94 | MT_DEVICE | MT_RW | MT_SECURE), |
| 95 | {0} |
| 96 | }; |
| 97 | |
| 98 | /******************************************************************************* |
| 99 | * Set up the pagetables as per the platform memory map & initialize the MMU |
| 100 | ******************************************************************************/ |
| 101 | const mmap_region_t *plat_get_mmio_map(void) |
| 102 | { |
| 103 | /* MMIO space */ |
| 104 | return tegra_mmap; |
| 105 | } |
| 106 | |
| 107 | /******************************************************************************* |
| 108 | * Handler to get the System Counter Frequency |
| 109 | ******************************************************************************/ |
Varun Wadekar | ef8a4fe | 2016-06-02 14:26:13 -0700 | [diff] [blame] | 110 | unsigned int plat_get_syscnt_freq2(void) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 111 | { |
Varun Wadekar | 20c9429 | 2016-01-04 10:57:45 -0800 | [diff] [blame] | 112 | return 31250000; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | /******************************************************************************* |
| 116 | * Maximum supported UART controllers |
| 117 | ******************************************************************************/ |
| 118 | #define TEGRA186_MAX_UART_PORTS 7 |
| 119 | |
| 120 | /******************************************************************************* |
| 121 | * This variable holds the UART port base addresses |
| 122 | ******************************************************************************/ |
| 123 | static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { |
| 124 | 0, /* undefined - treated as an error case */ |
| 125 | TEGRA_UARTA_BASE, |
| 126 | TEGRA_UARTB_BASE, |
| 127 | TEGRA_UARTC_BASE, |
| 128 | TEGRA_UARTD_BASE, |
| 129 | TEGRA_UARTE_BASE, |
| 130 | TEGRA_UARTF_BASE, |
| 131 | TEGRA_UARTG_BASE, |
| 132 | }; |
| 133 | |
| 134 | /******************************************************************************* |
| 135 | * Retrieve the UART controller base to be used as the console |
| 136 | ******************************************************************************/ |
| 137 | uint32_t plat_get_console_from_id(int id) |
| 138 | { |
| 139 | if (id > TEGRA186_MAX_UART_PORTS) |
| 140 | return 0; |
| 141 | |
| 142 | return tegra186_uart_addresses[id]; |
| 143 | } |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 144 | |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 145 | /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ |
| 146 | #define TEGRA186_VER_A02P 0x1201 |
| 147 | |
| 148 | /******************************************************************************* |
| 149 | * Handler for early platform setup |
| 150 | ******************************************************************************/ |
| 151 | void plat_early_platform_setup(void) |
| 152 | { |
| 153 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | 5887c10 | 2016-07-19 11:29:40 -0700 | [diff] [blame] | 154 | uint32_t chip_subrev, val; |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 155 | |
| 156 | /* sanity check MCE firmware compatibility */ |
| 157 | mce_verify_firmware_version(); |
| 158 | |
| 159 | /* |
| 160 | * Enable ECC and Parity Protection for Cortex-A57 CPUs |
| 161 | * for Tegra A02p SKUs |
| 162 | */ |
| 163 | if (impl != DENVER_IMPL) { |
| 164 | |
| 165 | /* get the major, minor and sub-version values */ |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 166 | chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & |
| 167 | SUBREVISION_MASK; |
| 168 | |
| 169 | /* prepare chip version number */ |
Varun Wadekar | 5887c10 | 2016-07-19 11:29:40 -0700 | [diff] [blame] | 170 | val = (tegra_get_chipid_major() << 12) | |
| 171 | (tegra_get_chipid_minor() << 8) | |
| 172 | chip_subrev; |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 173 | |
| 174 | /* enable L2 ECC for Tegra186 A02P and beyond */ |
| 175 | if (val >= TEGRA186_VER_A02P) { |
| 176 | |
| 177 | val = read_l2ctlr_el1(); |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 178 | val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 179 | write_l2ctlr_el1(val); |
| 180 | |
| 181 | /* |
| 182 | * Set the flag to enable ECC/Parity Protection |
| 183 | * when we exit System Suspend or Cluster Powerdn |
| 184 | */ |
| 185 | tegra_enable_l2_ecc_parity_prot = 1; |
| 186 | } |
| 187 | } |
| 188 | } |
| 189 | |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 190 | /* Secure IRQs for Tegra186 */ |
Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 191 | static const interrupt_prop_t tegra186_interrupt_props[] = { |
| 192 | INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, |
| 193 | GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), |
| 194 | INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, |
| 195 | GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | /******************************************************************************* |
| 199 | * Initialize the GIC and SGIs |
| 200 | ******************************************************************************/ |
| 201 | void plat_gic_setup(void) |
| 202 | { |
Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 203 | tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 204 | |
| 205 | /* |
| 206 | * Initialize the FIQ handler only if the platform supports any |
| 207 | * FIQ interrupt sources. |
| 208 | */ |
Varun Wadekar | 9f4a7d3 | 2018-10-19 11:42:28 -0700 | [diff] [blame] | 209 | if (sizeof(tegra186_interrupt_props) > 0) |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 210 | tegra_fiq_handler_setup(); |
| 211 | } |
Varun Wadekar | 94701ff | 2016-05-23 11:47:34 -0700 | [diff] [blame] | 212 | |
| 213 | /******************************************************************************* |
| 214 | * Return pointer to the BL31 params from previous bootloader |
| 215 | ******************************************************************************/ |
Antonio Nino Diaz | 6bf7c6b | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 216 | struct tegra_bl31_params *plat_get_bl31_params(void) |
Varun Wadekar | 94701ff | 2016-05-23 11:47:34 -0700 | [diff] [blame] | 217 | { |
| 218 | uint32_t val; |
| 219 | |
| 220 | val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); |
| 221 | |
Antonio Nino Diaz | 6bf7c6b | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 222 | return (struct tegra_bl31_params *)(uintptr_t)val; |
Varun Wadekar | 94701ff | 2016-05-23 11:47:34 -0700 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | /******************************************************************************* |
| 226 | * Return pointer to the BL31 platform params from previous bootloader |
| 227 | ******************************************************************************/ |
| 228 | plat_params_from_bl2_t *plat_get_bl31_plat_params(void) |
| 229 | { |
| 230 | uint32_t val; |
| 231 | |
| 232 | val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); |
| 233 | |
| 234 | return (plat_params_from_bl2_t *)(uintptr_t)val; |
| 235 | } |
Varun Wadekar | 43dad67 | 2017-01-31 14:53:37 -0800 | [diff] [blame] | 236 | |
| 237 | /******************************************************************************* |
| 238 | * This function implements a part of the critical interface between the psci |
| 239 | * generic layer and the platform that allows the former to query the platform |
| 240 | * to convert an MPIDR to a unique linear index. An error code (-1) is returned |
| 241 | * in case the MPIDR is invalid. |
| 242 | ******************************************************************************/ |
| 243 | int plat_core_pos_by_mpidr(u_register_t mpidr) |
| 244 | { |
| 245 | unsigned int cluster_id, cpu_id, pos; |
| 246 | |
| 247 | cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 248 | cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; |
| 249 | |
| 250 | /* |
| 251 | * Validate cluster_id by checking whether it represents |
| 252 | * one of the two clusters present on the platform. |
| 253 | */ |
| 254 | if (cluster_id >= PLATFORM_CLUSTER_COUNT) |
| 255 | return PSCI_E_NOT_PRESENT; |
| 256 | |
| 257 | /* |
| 258 | * Validate cpu_id by checking whether it represents a CPU in |
| 259 | * one of the two clusters present on the platform. |
| 260 | */ |
| 261 | if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) |
| 262 | return PSCI_E_NOT_PRESENT; |
| 263 | |
| 264 | /* calculate the core position */ |
| 265 | pos = cpu_id + (cluster_id << 2); |
| 266 | |
| 267 | /* check for non-existent CPUs */ |
| 268 | if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) |
| 269 | return PSCI_E_NOT_PRESENT; |
| 270 | |
| 271 | return pos; |
| 272 | } |