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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekar9f4a7d32018-10-19 11:42:28 -07002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05305 */
6
Varun Wadekarcad7b082015-12-28 18:12:59 -08007#include <arch_helpers.h>
8#include <assert.h>
Varun Wadekar94701ff2016-05-23 11:47:34 -07009#include <bl31.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080010#include <bl_common.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053011#include <console.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080012#include <context.h>
13#include <context_mgmt.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070014#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080015#include <debug.h>
16#include <denver.h>
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070017#include <gic_common.h>
18#include <gicv2.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080019#include <interrupt_mgmt.h>
Varun Wadekar9f4a7d32018-10-19 11:42:28 -070020#include <interrupt_props.h>
Varun Wadekar47ddd002016-03-28 16:00:02 -070021#include <mce.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080022#include <platform.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053023#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070024#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080025#include <tegra_private.h>
Andreas Färber92cea4a2018-02-17 06:02:32 +010026#include <xlat_tables_v2.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053027
Varun Wadekar1384a162017-06-05 14:54:46 -070028DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
Varun Wadekar4debe052016-05-18 13:39:16 -070029extern uint64_t tegra_enable_l2_ecc_parity_prot;
30
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080031/*******************************************************************************
Varun Wadekar43dad672017-01-31 14:53:37 -080032 * Tegra186 CPU numbers in cluster #0
33 *******************************************************************************
34 */
35#define TEGRA186_CLUSTER0_CORE2 2
36#define TEGRA186_CLUSTER0_CORE3 3
37
38/*******************************************************************************
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080039 * The Tegra power domain tree has a single system level power domain i.e. a
40 * single root node. The first entry in the power domain descriptor specifies
41 * the number of power domains at the highest power level.
42 *******************************************************************************
43 */
44const unsigned char tegra_power_domain_tree_desc[] = {
45 /* No of root nodes */
46 1,
47 /* No of clusters */
48 PLATFORM_CLUSTER_COUNT,
49 /* No of CPU cores - cluster0 */
50 PLATFORM_MAX_CPUS_PER_CLUSTER,
51 /* No of CPU cores - cluster1 */
52 PLATFORM_MAX_CPUS_PER_CLUSTER
53};
54
Varun Wadekar921b9062015-08-25 17:03:14 +053055/*
56 * Table of regions to map using the MMU.
57 */
58static const mmap_region_t tegra_mmap[] = {
59 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
60 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekara0f26972016-03-11 17:18:51 -080061 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
62 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053063 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
64 MT_DEVICE | MT_RW | MT_SECURE),
65 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
66 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar9db0ad12016-07-12 10:04:28 -070067 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
68 MT_DEVICE | MT_RW | MT_SECURE),
69 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
70 MT_DEVICE | MT_RW | MT_SECURE),
71 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053072 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar4debe052016-05-18 13:39:16 -070073 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
74 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053075 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
76 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -080077 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
78 MT_DEVICE | MT_RW | MT_SECURE),
79 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
80 MT_DEVICE | MT_RW | MT_SECURE),
81 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
82 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekare60f1bf2016-02-17 10:10:50 -080083 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
84 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053085 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
86 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -080087 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
88 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053089 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
90 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekard64db962016-09-23 14:28:16 -070091 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
92 MT_DEVICE | MT_RW | MT_SECURE),
Pritesh Raithatha0de6e532017-01-24 13:49:46 +053093 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053094 MT_DEVICE | MT_RW | MT_SECURE),
95 {0}
96};
97
98/*******************************************************************************
99 * Set up the pagetables as per the platform memory map & initialize the MMU
100 ******************************************************************************/
101const mmap_region_t *plat_get_mmio_map(void)
102{
103 /* MMIO space */
104 return tegra_mmap;
105}
106
107/*******************************************************************************
108 * Handler to get the System Counter Frequency
109 ******************************************************************************/
Varun Wadekaref8a4fe2016-06-02 14:26:13 -0700110unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530111{
Varun Wadekar20c94292016-01-04 10:57:45 -0800112 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530113}
114
115/*******************************************************************************
116 * Maximum supported UART controllers
117 ******************************************************************************/
118#define TEGRA186_MAX_UART_PORTS 7
119
120/*******************************************************************************
121 * This variable holds the UART port base addresses
122 ******************************************************************************/
123static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
124 0, /* undefined - treated as an error case */
125 TEGRA_UARTA_BASE,
126 TEGRA_UARTB_BASE,
127 TEGRA_UARTC_BASE,
128 TEGRA_UARTD_BASE,
129 TEGRA_UARTE_BASE,
130 TEGRA_UARTF_BASE,
131 TEGRA_UARTG_BASE,
132};
133
134/*******************************************************************************
135 * Retrieve the UART controller base to be used as the console
136 ******************************************************************************/
137uint32_t plat_get_console_from_id(int id)
138{
139 if (id > TEGRA186_MAX_UART_PORTS)
140 return 0;
141
142 return tegra186_uart_addresses[id];
143}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800144
Varun Wadekar4debe052016-05-18 13:39:16 -0700145/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
146#define TEGRA186_VER_A02P 0x1201
147
148/*******************************************************************************
149 * Handler for early platform setup
150 ******************************************************************************/
151void plat_early_platform_setup(void)
152{
153 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
Varun Wadekar5887c102016-07-19 11:29:40 -0700154 uint32_t chip_subrev, val;
Varun Wadekar4debe052016-05-18 13:39:16 -0700155
156 /* sanity check MCE firmware compatibility */
157 mce_verify_firmware_version();
158
159 /*
160 * Enable ECC and Parity Protection for Cortex-A57 CPUs
161 * for Tegra A02p SKUs
162 */
163 if (impl != DENVER_IMPL) {
164
165 /* get the major, minor and sub-version values */
Varun Wadekar4debe052016-05-18 13:39:16 -0700166 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
167 SUBREVISION_MASK;
168
169 /* prepare chip version number */
Varun Wadekar5887c102016-07-19 11:29:40 -0700170 val = (tegra_get_chipid_major() << 12) |
171 (tegra_get_chipid_minor() << 8) |
172 chip_subrev;
Varun Wadekar4debe052016-05-18 13:39:16 -0700173
174 /* enable L2 ECC for Tegra186 A02P and beyond */
175 if (val >= TEGRA186_VER_A02P) {
176
177 val = read_l2ctlr_el1();
Varun Wadekar1384a162017-06-05 14:54:46 -0700178 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
Varun Wadekar4debe052016-05-18 13:39:16 -0700179 write_l2ctlr_el1(val);
180
181 /*
182 * Set the flag to enable ECC/Parity Protection
183 * when we exit System Suspend or Cluster Powerdn
184 */
185 tegra_enable_l2_ecc_parity_prot = 1;
186 }
187 }
188}
189
Varun Wadekarcad7b082015-12-28 18:12:59 -0800190/* Secure IRQs for Tegra186 */
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700191static const interrupt_prop_t tegra186_interrupt_props[] = {
192 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
193 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
194 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
195 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarcad7b082015-12-28 18:12:59 -0800196};
197
198/*******************************************************************************
199 * Initialize the GIC and SGIs
200 ******************************************************************************/
201void plat_gic_setup(void)
202{
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700203 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
Varun Wadekarcad7b082015-12-28 18:12:59 -0800204
205 /*
206 * Initialize the FIQ handler only if the platform supports any
207 * FIQ interrupt sources.
208 */
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700209 if (sizeof(tegra186_interrupt_props) > 0)
Varun Wadekarcad7b082015-12-28 18:12:59 -0800210 tegra_fiq_handler_setup();
211}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700212
213/*******************************************************************************
214 * Return pointer to the BL31 params from previous bootloader
215 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100216struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekar94701ff2016-05-23 11:47:34 -0700217{
218 uint32_t val;
219
220 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
221
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100222 return (struct tegra_bl31_params *)(uintptr_t)val;
Varun Wadekar94701ff2016-05-23 11:47:34 -0700223}
224
225/*******************************************************************************
226 * Return pointer to the BL31 platform params from previous bootloader
227 ******************************************************************************/
228plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
229{
230 uint32_t val;
231
232 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
233
234 return (plat_params_from_bl2_t *)(uintptr_t)val;
235}
Varun Wadekar43dad672017-01-31 14:53:37 -0800236
237/*******************************************************************************
238 * This function implements a part of the critical interface between the psci
239 * generic layer and the platform that allows the former to query the platform
240 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
241 * in case the MPIDR is invalid.
242 ******************************************************************************/
243int plat_core_pos_by_mpidr(u_register_t mpidr)
244{
245 unsigned int cluster_id, cpu_id, pos;
246
247 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
248 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
249
250 /*
251 * Validate cluster_id by checking whether it represents
252 * one of the two clusters present on the platform.
253 */
254 if (cluster_id >= PLATFORM_CLUSTER_COUNT)
255 return PSCI_E_NOT_PRESENT;
256
257 /*
258 * Validate cpu_id by checking whether it represents a CPU in
259 * one of the two clusters present on the platform.
260 */
261 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
262 return PSCI_E_NOT_PRESENT;
263
264 /* calculate the core position */
265 pos = cpu_id + (cluster_id << 2);
266
267 /* check for non-existent CPUs */
268 if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
269 return PSCI_E_NOT_PRESENT;
270
271 return pos;
272}