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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +05302 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -07003 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05305 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef VERSAL_DEF_H
10#define VERSAL_DEF_H
11
Manish V Badarkhe55861512020-03-27 13:25:51 +000012#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <plat/common/common_def.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053014
Tanmay Shahfdae9e82022-08-26 15:06:00 -070015/* number of interrupt handlers. increase as required */
16#define MAX_INTR_EL3 2
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053017/* List all consoles */
18#define VERSAL_CONSOLE_ID_pl011 1
19#define VERSAL_CONSOLE_ID_pl011_0 1
20#define VERSAL_CONSOLE_ID_pl011_1 2
21#define VERSAL_CONSOLE_ID_dcc 3
22
23#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
24
25/* List all supported platforms */
26#define VERSAL_PLATFORM_ID_versal_virt 1
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053027#define VERSAL_PLATFORM_ID_spp_itr6 2
28#define VERSAL_PLATFORM_ID_emu_itr6 3
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053029#define VERSAL_PLATFORM_ID_silicon 4
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053030
31#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
32
33/* Firmware Image Package */
34#define VERSAL_PRIMARY_CPU 0
35
36/*******************************************************************************
37 * memory map related constants
38 ******************************************************************************/
39#define DEVICE0_BASE 0xFF000000
40#define DEVICE0_SIZE 0x00E00000
41#define DEVICE1_BASE 0xF9000000
42#define DEVICE1_SIZE 0x00800000
43
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053044/*******************************************************************************
45 * IRQ constants
46 ******************************************************************************/
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -070047#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053048
49/*******************************************************************************
Tejas Patel54d13192019-02-27 18:44:55 +053050 * CCI-400 related constants
51 ******************************************************************************/
52#define PLAT_ARM_CCI_BASE 0xFD000000
53#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
54#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
55
56/*******************************************************************************
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053057 * UART related constants
58 ******************************************************************************/
59#define VERSAL_UART0_BASE 0xFF000000
60#define VERSAL_UART1_BASE 0xFF010000
61
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070062#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053063# define VERSAL_UART_BASE VERSAL_UART0_BASE
64#elif VERSAL_CONSOLE_IS(pl011_1)
65# define VERSAL_UART_BASE VERSAL_UART1_BASE
66#else
67# error "invalid VERSAL_CONSOLE"
68#endif
69
70#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
71#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
72#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
73
74/*******************************************************************************
75 * Platform related constants
76 ******************************************************************************/
77#if VERSAL_PLATFORM_IS(versal_virt)
78# define PLATFORM_NAME "Versal Virt"
79# define VERSAL_UART_CLOCK 25000000
80# define VERSAL_UART_BAUDRATE 115200
Siva Durga Prasad Paladugu10161e52019-04-27 11:23:20 +053081# define VERSAL_CPU_CLOCK 2720000
Siva Durga Prasad Paladugu2f4cc712019-05-03 16:35:25 +053082#elif VERSAL_PLATFORM_IS(silicon)
83# define PLATFORM_NAME "Versal Silicon"
84# define VERSAL_UART_CLOCK 100000000
85# define VERSAL_UART_BAUDRATE 115200
86# define VERSAL_CPU_CLOCK 100000000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053087#elif VERSAL_PLATFORM_IS(spp_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053088# define PLATFORM_NAME "SPP ITR6"
89# define VERSAL_UART_CLOCK 25000000
90# define VERSAL_UART_BAUDRATE 115200
91# define VERSAL_CPU_CLOCK 2720000
Venkatesh Yadav Abbarapu9c3b77b2022-04-13 09:04:53 +053092#elif VERSAL_PLATFORM_IS(emu_itr6)
Venkatesh Yadav Abbarapud90e47b2022-07-28 08:50:30 +053093# define PLATFORM_NAME "EMU ITR6"
94# define VERSAL_UART_CLOCK 212000
95# define VERSAL_UART_BAUDRATE 9600
96# define VERSAL_CPU_CLOCK 212000
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053097#endif
98
99/* Access control register defines */
100#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
101#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
102
103/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
104#define CRF_BASE 0xFD1A0000
105#define CRF_SIZE 0x00600000
106
107/* CRF registers and bitfields */
108#define CRF_RST_APU (CRF_BASE + 0X00000300)
109
110#define CRF_RST_APU_ACPU_RESET (1 << 0)
111#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
112
Tejas Patel54d13192019-02-27 18:44:55 +0530113#define FPD_MAINCCI_BASE 0xFD000000
114#define FPD_MAINCCI_SIZE 0x00100000
115
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530116/* APU registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700117#define FPD_APU_BASE 0xFD5C0000U
118#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
119#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
120#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
121#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530122
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700123#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
124#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
125#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530126
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700127/* PMC registers and bitfields */
Abhyuday Godhasaraedc38ae2021-08-04 23:58:46 -0700128#define PMC_GLOBAL_BASE 0xF1110000U
129#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700130
Tejas Patel354fe572018-12-14 00:55:37 -0800131/* IPI registers and bitfields */
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700132#define IPI0_REG_BASE U(0xFF330000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700133#define IPI0_TRIG_BIT (1U << 2U)
134#define PMC_IPI_TRIG_BIT (1U << 1U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700135#define IPI1_REG_BASE U(0xFF340000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700136#define IPI1_TRIG_BIT (1U << 3U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700137#define IPI2_REG_BASE U(0xFF350000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700138#define IPI2_TRIG_BIT (1U << 4U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700139#define IPI3_REG_BASE U(0xFF360000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700140#define IPI3_TRIG_BIT (1U << 5U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700141#define IPI4_REG_BASE U(0xFF370000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700142#define IPI4_TRIG_BIT (1U << 5U)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700143#define IPI5_REG_BASE U(0xFF380000)
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700144#define IPI5_TRIG_BIT (1U << 6U)
Tejas Patel354fe572018-12-14 00:55:37 -0800145
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530146#endif /* VERSAL_DEF_H */