| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 1 | /* |
| Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> |
| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MSM8916_MMAP_H |
| 8 | #define MSM8916_MMAP_H |
| 9 | |
| 10 | #define PCNOC_BASE 0x00000000 |
| Stephan Gerhold | 20e84c8 | 2023-03-26 13:07:25 +0200 | [diff] [blame] | 11 | #define PCNOC_SIZE SZ_128M |
| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 12 | #define APCS_BASE 0x0b000000 |
| Stephan Gerhold | 20e84c8 | 2023-03-26 13:07:25 +0200 | [diff] [blame] | 13 | #define APCS_SIZE SZ_8M |
| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 14 | |
| 15 | #define MPM_BASE (PCNOC_BASE + 0x04a0000) |
| 16 | #define MPM_PS_HOLD (MPM_BASE + 0xb000) |
| 17 | |
| 18 | #define TLMM_BASE (PCNOC_BASE + 0x1000000) |
| 19 | #define TLMM_GPIO_CFG(n) (TLMM_BASE + ((n) * 0x1000)) |
| 20 | |
| 21 | #define GCC_BASE (PCNOC_BASE + 0x1800000) |
| 22 | |
| Stephan Gerhold | 253fef0 | 2021-12-01 20:03:33 +0100 | [diff] [blame] | 23 | #define APPS_SMMU_BASE (PCNOC_BASE + 0x1e00000) |
| 24 | #define APPS_SMMU_QCOM (APPS_SMMU_BASE + 0xf0000) |
| Stephan Gerhold | 419ebb8 | 2023-03-15 09:24:49 +0100 | [diff] [blame] | 25 | #define GPU_SMMU_BASE (PCNOC_BASE + 0x1f00000) |
| Stephan Gerhold | 253fef0 | 2021-12-01 20:03:33 +0100 | [diff] [blame] | 26 | |
| Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 27 | #define BLSP1_BASE (PCNOC_BASE + 0x7880000) |
| 28 | #define BLSP1_UART_BASE(n) (BLSP1_BASE + 0x2f000 + (((n) - 1) * 0x1000)) |
| 29 | #define BLSP_UART_BASE BLSP1_UART_BASE(QTI_UART_NUM) |
| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 30 | |
| 31 | #define APCS_QGIC2_BASE (APCS_BASE + 0x00000) |
| 32 | #define APCS_QGIC2_GICD (APCS_QGIC2_BASE + 0x0000) |
| 33 | #define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000) |
| 34 | #define APCS_BANKED_ACS (APCS_BASE + 0x08000) |
| 35 | #define APCS_BANKED_SAW2 (APCS_BASE + 0x09000) |
| Stephan Gerhold | f0ed728 | 2022-09-16 10:45:19 +0200 | [diff] [blame] | 36 | |
| 37 | #define _APCS_CLUSTER(cluster) (APCS_BASE + ((cluster) * 0x100000)) |
| 38 | #define _APCS_CPU(cluster, cpu) (_APCS_CLUSTER(cluster) + ((cpu) * 0x10000)) |
| 39 | #define APCS_CFG(cluster) (_APCS_CLUSTER(cluster) + 0x10000) |
| 40 | #define APCS_GLB(cluster) (_APCS_CLUSTER(cluster) + 0x11000) |
| 41 | #define APCS_L2_SAW2(cluster) (_APCS_CLUSTER(cluster) + 0x12000) |
| 42 | #define APCS_QTMR(cluster) (_APCS_CLUSTER(cluster) + 0x20000) |
| 43 | #define APCS_ALIAS_ACS(cluster, cpu) (_APCS_CPU(cluster, cpu) + 0x88000) |
| 44 | #define APCS_ALIAS_SAW2(cluster, cpu) (_APCS_CPU(cluster, cpu) + 0x89000) |
| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 45 | |
| Stephan Gerhold | 1b78346 | 2022-09-16 20:42:49 +0200 | [diff] [blame] | 46 | /* Only on platforms with multiple clusters (e.g. MSM8939) */ |
| 47 | #define APCS_CCI_BASE (APCS_BASE + 0x1c0000) |
| 48 | #define APCS_CCI_SAW2 (APCS_BASE + 0x1d2000) |
| 49 | #define APCS_CCI_ACS (APCS_BASE + 0x1d4000) |
| 50 | |
| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 51 | #endif /* MSM8916_MMAP_H */ |