| Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MSM8916_MMAP_H |
| 8 | #define MSM8916_MMAP_H |
| 9 | |
| 10 | #define PCNOC_BASE 0x00000000 |
| 11 | #define PCNOC_SIZE 0x8000000 /* 128 MiB */ |
| 12 | #define APCS_BASE 0x0b000000 |
| 13 | #define APCS_SIZE 0x800000 /* 8 MiB */ |
| 14 | |
| 15 | #define MPM_BASE (PCNOC_BASE + 0x04a0000) |
| 16 | #define MPM_PS_HOLD (MPM_BASE + 0xb000) |
| 17 | |
| 18 | #define TLMM_BASE (PCNOC_BASE + 0x1000000) |
| 19 | #define TLMM_GPIO_CFG(n) (TLMM_BASE + ((n) * 0x1000)) |
| 20 | |
| 21 | #define GCC_BASE (PCNOC_BASE + 0x1800000) |
| 22 | |
| 23 | #define BLSP_UART1_BASE (PCNOC_BASE + 0x78af000) |
| 24 | #define BLSP_UART2_BASE (PCNOC_BASE + 0x78b0000) |
| 25 | |
| 26 | #define APCS_QGIC2_BASE (APCS_BASE + 0x00000) |
| 27 | #define APCS_QGIC2_GICD (APCS_QGIC2_BASE + 0x0000) |
| 28 | #define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000) |
| 29 | #define APCS_BANKED_ACS (APCS_BASE + 0x08000) |
| 30 | #define APCS_BANKED_SAW2 (APCS_BASE + 0x09000) |
| 31 | #define APCS_CFG (APCS_BASE + 0x10000) |
| 32 | #define APCS_GLB (APCS_BASE + 0x11000) |
| 33 | #define APCS_L2_SAW2 (APCS_BASE + 0x12000) |
| 34 | #define APCS_QTMR (APCS_BASE + 0x20000) |
| 35 | #define APCS_ALIAS_ACS(cpu) (APCS_BASE + 0x88000 + ((cpu) * 0x10000)) |
| 36 | #define APCS_ALIAS_SAW2(cpu) (APCS_BASE + 0x89000 + ((cpu) * 0x10000)) |
| 37 | |
| 38 | #endif /* MSM8916_MMAP_H */ |