blob: d2015368239be1c9f529f2f7da34082c06d35dec [file] [log] [blame]
Stephan Gerhold14fdf072021-12-01 20:01:11 +01001/*
2 * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MSM8916_MMAP_H
8#define MSM8916_MMAP_H
9
10#define PCNOC_BASE 0x00000000
Stephan Gerhold20e84c82023-03-26 13:07:25 +020011#define PCNOC_SIZE SZ_128M
Stephan Gerhold14fdf072021-12-01 20:01:11 +010012#define APCS_BASE 0x0b000000
Stephan Gerhold20e84c82023-03-26 13:07:25 +020013#define APCS_SIZE SZ_8M
Stephan Gerhold14fdf072021-12-01 20:01:11 +010014
15#define MPM_BASE (PCNOC_BASE + 0x04a0000)
16#define MPM_PS_HOLD (MPM_BASE + 0xb000)
17
18#define TLMM_BASE (PCNOC_BASE + 0x1000000)
19#define TLMM_GPIO_CFG(n) (TLMM_BASE + ((n) * 0x1000))
20
21#define GCC_BASE (PCNOC_BASE + 0x1800000)
22
Stephan Gerhold253fef02021-12-01 20:03:33 +010023#define APPS_SMMU_BASE (PCNOC_BASE + 0x1e00000)
24#define APPS_SMMU_QCOM (APPS_SMMU_BASE + 0xf0000)
25
Stephan Gerhold14fdf072021-12-01 20:01:11 +010026#define BLSP_UART1_BASE (PCNOC_BASE + 0x78af000)
27#define BLSP_UART2_BASE (PCNOC_BASE + 0x78b0000)
28
29#define APCS_QGIC2_BASE (APCS_BASE + 0x00000)
30#define APCS_QGIC2_GICD (APCS_QGIC2_BASE + 0x0000)
31#define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000)
32#define APCS_BANKED_ACS (APCS_BASE + 0x08000)
33#define APCS_BANKED_SAW2 (APCS_BASE + 0x09000)
34#define APCS_CFG (APCS_BASE + 0x10000)
35#define APCS_GLB (APCS_BASE + 0x11000)
36#define APCS_L2_SAW2 (APCS_BASE + 0x12000)
37#define APCS_QTMR (APCS_BASE + 0x20000)
38#define APCS_ALIAS_ACS(cpu) (APCS_BASE + 0x88000 + ((cpu) * 0x10000))
39#define APCS_ALIAS_SAW2(cpu) (APCS_BASE + 0x89000 + ((cpu) * 0x10000))
40
41#endif /* MSM8916_MMAP_H */