Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
Varun Wadekar | 4edc17c | 2017-11-20 17:14:47 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 8 | #include <assert.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 9 | #include <stdbool.h> |
| 10 | #include <string.h> |
| 11 | |
| 12 | #include <arch_helpers.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 13 | #include <common/bl_common.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 14 | #include <common/debug.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 15 | #include <context.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 16 | #include <denver.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 17 | #include <lib/el3_runtime/context_mgmt.h> |
| 18 | #include <lib/psci/psci.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 19 | #include <mce.h> |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 20 | #include <mce_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 21 | #include <plat/common/platform.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 22 | #include <se.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 23 | #include <smmu.h> |
Tejal Kudav | 153ba22 | 2017-02-14 18:02:04 -0800 | [diff] [blame] | 24 | #include <t194_nvg.h> |
Varun Wadekar | e0c222f | 2017-11-10 13:23:34 -0800 | [diff] [blame] | 25 | #include <tegra194_private.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 26 | #include <tegra_platform.h> |
| 27 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 28 | |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 29 | extern uint32_t __tegra194_cpu_reset_handler_data, |
| 30 | __tegra194_cpu_reset_handler_end; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 31 | |
| 32 | /* TZDRAM offset for saving SMMU context */ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 33 | #define TEGRA194_SMMU_CTX_OFFSET 16U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 34 | |
| 35 | /* state id mask */ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 36 | #define TEGRA194_STATE_ID_MASK 0xFU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 37 | /* constants to get power state's wake time */ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 38 | #define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U |
| 39 | #define TEGRA194_WAKE_TIME_SHIFT 4U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 40 | /* default core wake mask for CPU_SUSPEND */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 41 | #define TEGRA194_CORE_WAKE_MASK 0x180cU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 42 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 43 | static struct t19x_psci_percpu_data { |
| 44 | uint32_t wake_time; |
| 45 | } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 46 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 47 | int32_t tegra_soc_validate_power_state(uint32_t power_state, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 48 | psci_power_state_t *req_state) |
| 49 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 50 | uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 51 | TEGRA194_STATE_ID_MASK; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 52 | uint32_t cpu = plat_my_core_pos(); |
| 53 | int32_t ret = PSCI_E_SUCCESS; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 54 | |
| 55 | /* save the core wake time (in TSC ticks)*/ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 56 | t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK) |
| 57 | << TEGRA194_WAKE_TIME_SHIFT; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 58 | |
| 59 | /* |
Varun Wadekar | 56c6459 | 2019-12-03 08:50:57 -0800 | [diff] [blame] | 60 | * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure |
| 61 | * that the correct value is read in tegra_soc_pwr_domain_suspend(), |
| 62 | * which is called with caches disabled. It is possible to read a stale |
| 63 | * value from DRAM in that function, because the L2 cache is not flushed |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 64 | * unless the cluster is entering CC6/CC7. |
| 65 | */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 66 | clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], |
| 67 | sizeof(t19x_percpu_data[cpu])); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 68 | |
| 69 | /* Sanity check the requested state id */ |
| 70 | switch (state_id) { |
| 71 | case PSTATE_ID_CORE_IDLE: |
Varun Wadekar | c61094b | 2017-12-27 18:01:59 -0800 | [diff] [blame] | 72 | |
| 73 | /* Core idle request */ |
| 74 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; |
| 75 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN; |
| 76 | break; |
| 77 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 78 | case PSTATE_ID_CORE_POWERDN: |
| 79 | |
| 80 | /* Core powerdown request */ |
| 81 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
| 82 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
| 83 | |
| 84 | break; |
| 85 | |
| 86 | default: |
| 87 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 88 | ret = PSCI_E_INVALID_PARAMS; |
| 89 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 92 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 93 | } |
| 94 | |
Varun Wadekar | c61094b | 2017-12-27 18:01:59 -0800 | [diff] [blame] | 95 | int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state) |
| 96 | { |
| 97 | uint32_t cpu = plat_my_core_pos(); |
| 98 | mce_cstate_info_t cstate_info = { 0 }; |
| 99 | |
| 100 | /* Program default wake mask */ |
| 101 | cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; |
| 102 | cstate_info.update_wake_mask = 1; |
| 103 | mce_update_cstate_info(&cstate_info); |
| 104 | |
| 105 | /* Enter CPU idle */ |
| 106 | (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, |
| 107 | (uint64_t)TEGRA_NVG_CORE_C6, |
| 108 | t19x_percpu_data[cpu].wake_time, |
| 109 | 0U); |
| 110 | |
| 111 | return PSCI_E_SUCCESS; |
| 112 | } |
| 113 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 114 | int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 115 | { |
| 116 | const plat_local_state_t *pwr_domain_state; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 117 | uint8_t stateid_afflvl0, stateid_afflvl2; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 118 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 119 | uint64_t smmu_ctx_base; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 120 | uint32_t val; |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 121 | mce_cstate_info_t sc7_cstate_info = { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 122 | .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, |
Vignesh Radhakrishnan | 85c129f | 2017-12-20 15:04:26 -0800 | [diff] [blame] | 123 | .ccplex = (uint32_t)TEGRA_NVG_CG_CG7, |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 124 | .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, |
| 125 | .system_state_force = 1U, |
| 126 | .update_wake_mask = 1U, |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 127 | }; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 128 | uint32_t cpu = plat_my_core_pos(); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 129 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 130 | |
| 131 | /* get the state ID */ |
| 132 | pwr_domain_state = target_state->pwr_domain_state; |
| 133 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 134 | TEGRA194_STATE_ID_MASK; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 135 | stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 136 | TEGRA194_STATE_ID_MASK; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 137 | |
Varun Wadekar | c61094b | 2017-12-27 18:01:59 -0800 | [diff] [blame] | 138 | if ((stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 139 | |
Varun Wadekar | c61094b | 2017-12-27 18:01:59 -0800 | [diff] [blame] | 140 | /* Enter CPU powerdown */ |
| 141 | (void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, |
| 142 | (uint64_t)TEGRA_NVG_CORE_C7, |
| 143 | t19x_percpu_data[cpu].wake_time, |
| 144 | 0U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 145 | |
| 146 | } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 147 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 148 | /* save 'Secure Boot' Processor Feature Config Register */ |
| 149 | val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); |
Steven Kao | 4607f17 | 2017-10-23 18:35:14 +0800 | [diff] [blame] | 150 | mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 151 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 152 | /* save SMMU context */ |
| 153 | smmu_ctx_base = params_from_bl2->tzdram_base + |
Varun Wadekar | e0c222f | 2017-11-10 13:23:34 -0800 | [diff] [blame] | 154 | tegra194_get_smmu_ctx_offset(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 155 | tegra_smmu_save_context((uintptr_t)smmu_ctx_base); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 156 | |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 157 | /* |
| 158 | * Suspend SE, RNG1 and PKA1 only on silcon and fpga, |
| 159 | * since VDK does not support atomic se ctx save |
| 160 | */ |
| 161 | if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { |
| 162 | ret = tegra_se_suspend(); |
| 163 | assert(ret == 0); |
| 164 | } |
| 165 | |
Varun Wadekar | 953699c | 2018-06-06 17:26:10 -0700 | [diff] [blame] | 166 | /* Prepare for system suspend */ |
| 167 | mce_update_cstate_info(&sc7_cstate_info); |
Tejal Kudav | 153ba22 | 2017-02-14 18:02:04 -0800 | [diff] [blame] | 168 | |
Varun Wadekar | 953699c | 2018-06-06 17:26:10 -0700 | [diff] [blame] | 169 | do { |
| 170 | val = (uint32_t)mce_command_handler( |
| 171 | (uint32_t)MCE_CMD_IS_SC7_ALLOWED, |
| 172 | (uint32_t)TEGRA_NVG_CORE_C7, |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 173 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 174 | 0U); |
Varun Wadekar | 953699c | 2018-06-06 17:26:10 -0700 | [diff] [blame] | 175 | } while (val == 0U); |
Varun Wadekar | da865de | 2017-11-10 13:27:29 -0800 | [diff] [blame] | 176 | |
Varun Wadekar | 953699c | 2018-06-06 17:26:10 -0700 | [diff] [blame] | 177 | /* Instruct the MCE to enter system suspend state */ |
| 178 | ret = mce_command_handler( |
| 179 | (uint64_t)MCE_CMD_ENTER_CSTATE, |
| 180 | (uint64_t)TEGRA_NVG_CORE_C7, |
| 181 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 182 | 0U); |
| 183 | assert(ret == 0); |
| 184 | |
| 185 | /* set system suspend state for house-keeping */ |
| 186 | tegra194_set_system_suspend_entry(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 187 | } else { |
| 188 | ; /* do nothing */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 189 | } |
| 190 | |
| 191 | return PSCI_E_SUCCESS; |
| 192 | } |
| 193 | |
| 194 | /******************************************************************************* |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 195 | * Helper function to check if this is the last ON CPU in the cluster |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 196 | ******************************************************************************/ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 197 | static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, |
| 198 | uint32_t ncpu) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 199 | { |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 200 | plat_local_state_t target; |
| 201 | bool last_on_cpu = true; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 202 | uint32_t num_cpus = ncpu, pos = 0; |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 203 | |
| 204 | do { |
| 205 | target = states[pos]; |
| 206 | if (target != PLAT_MAX_OFF_STATE) { |
| 207 | last_on_cpu = false; |
| 208 | } |
| 209 | --num_cpus; |
| 210 | pos++; |
| 211 | } while (num_cpus != 0U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 212 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 213 | return last_on_cpu; |
| 214 | } |
| 215 | |
| 216 | /******************************************************************************* |
| 217 | * Helper function to get target power state for the cluster |
| 218 | ******************************************************************************/ |
| 219 | static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, |
| 220 | uint32_t ncpu) |
| 221 | { |
| 222 | uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; |
| 223 | plat_local_state_t target = states[core_pos]; |
| 224 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 225 | |
| 226 | /* CPU suspend */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 227 | if (target == PSTATE_ID_CORE_POWERDN) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 228 | |
| 229 | /* Program default wake mask */ |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 230 | cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; |
| 231 | cstate_info.update_wake_mask = 1; |
| 232 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | /* CPU off */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 236 | if (target == PLAT_MAX_OFF_STATE) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 237 | |
| 238 | /* Enable cluster powerdn from last CPU in the cluster */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 239 | if (tegra_last_on_cpu_in_cluster(states, ncpu)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 240 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 241 | /* Enable CC6 state and turn off wake mask */ |
| 242 | cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; |
Vignesh Radhakrishnan | 90d8019 | 2017-12-27 21:04:49 -0800 | [diff] [blame] | 243 | cstate_info.ccplex = (uint32_t)TEGRA_NVG_CG_CG7; |
| 244 | cstate_info.system_state_force = 1; |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 245 | cstate_info.update_wake_mask = 1U; |
| 246 | mce_update_cstate_info(&cstate_info); |
| 247 | |
| 248 | } else { |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 249 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 250 | /* Turn off wake_mask */ |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 251 | cstate_info.update_wake_mask = 1U; |
| 252 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 253 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 254 | } |
| 255 | } |
| 256 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 257 | return target; |
| 258 | } |
| 259 | |
| 260 | /******************************************************************************* |
| 261 | * Platform handler to calculate the proper target power level at the |
| 262 | * specified affinity level |
| 263 | ******************************************************************************/ |
| 264 | plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, |
| 265 | const plat_local_state_t *states, |
| 266 | uint32_t ncpu) |
| 267 | { |
| 268 | plat_local_state_t target = PSCI_LOCAL_STATE_RUN; |
| 269 | uint32_t cpu = plat_my_core_pos(); |
| 270 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 271 | /* System Suspend */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 272 | if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { |
| 273 | target = PSTATE_ID_SOC_POWERDN; |
| 274 | } |
| 275 | |
| 276 | /* CPU off, CPU suspend */ |
| 277 | if (lvl == (uint32_t)MPIDR_AFFLVL1) { |
| 278 | target = tegra_get_afflvl1_pwr_state(states, ncpu); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 279 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 280 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 281 | /* target cluster/system state */ |
| 282 | return target; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 283 | } |
| 284 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 285 | int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 286 | { |
| 287 | const plat_local_state_t *pwr_domain_state = |
| 288 | target_state->pwr_domain_state; |
| 289 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 290 | uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 291 | TEGRA194_STATE_ID_MASK; |
Steven Kao | 55c2ce7 | 2016-12-23 15:51:32 +0800 | [diff] [blame] | 292 | uint64_t val; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 293 | |
| 294 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 295 | /* |
| 296 | * The TZRAM loses power when we enter system suspend. To |
| 297 | * allow graceful exit from system suspend, we need to copy |
| 298 | * BL3-1 over to TZDRAM. |
| 299 | */ |
| 300 | val = params_from_bl2->tzdram_base + |
Varun Wadekar | e0c222f | 2017-11-10 13:23:34 -0800 | [diff] [blame] | 301 | tegra194_get_cpu_reset_handler_size(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 302 | memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, |
| 303 | (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); |
| 304 | } |
| 305 | |
| 306 | return PSCI_E_SUCCESS; |
| 307 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 308 | |
Varun Wadekar | b5b15b2 | 2018-05-17 10:10:25 -0700 | [diff] [blame] | 309 | int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
| 310 | { |
| 311 | return PSCI_E_NOT_SUPPORTED; |
| 312 | } |
| 313 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 314 | int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 315 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 316 | uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; |
| 317 | uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 318 | MPIDR_AFFINITY_BITS; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 319 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 320 | |
Varun Wadekar | a4e0a81 | 2017-10-17 10:53:33 -0700 | [diff] [blame] | 321 | if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 322 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); |
| 323 | return PSCI_E_NOT_PRESENT; |
| 324 | } |
| 325 | |
| 326 | /* construct the target CPU # */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 327 | target_cpu += (target_cluster << 1U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 328 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 329 | ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); |
| 330 | if (ret < 0) { |
| 331 | return PSCI_E_DENIED; |
| 332 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 333 | |
| 334 | return PSCI_E_SUCCESS; |
| 335 | } |
| 336 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 337 | int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 338 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 339 | uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 340 | |
| 341 | /* |
| 342 | * Reset power state info for CPUs when onlining, we set |
| 343 | * deepest power when offlining a core but that may not be |
| 344 | * requested by non-secure sw which controls idle states. It |
| 345 | * will re-init this info from non-secure software when the |
| 346 | * core come online. |
| 347 | */ |
| 348 | |
| 349 | /* |
| 350 | * Check if we are exiting from deep sleep and restore SE |
| 351 | * context if we are. |
| 352 | */ |
| 353 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 354 | |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 355 | #if ENABLE_STRICT_CHECKING_MODE |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 356 | /* |
| 357 | * Enable strict checking after programming the GSC for |
| 358 | * enabling TZSRAM and TZDRAM |
| 359 | */ |
| 360 | mce_enable_strict_checking(); |
Steven Kao | 8f4f102 | 2017-12-13 06:39:15 +0800 | [diff] [blame] | 361 | #endif |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 362 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 363 | /* Init SMMU */ |
Vignesh Radhakrishnan | 978887f | 2017-07-11 15:16:08 -0700 | [diff] [blame] | 364 | tegra_smmu_init(); |
| 365 | |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 366 | /* Resume SE, RNG1 and PKA1 */ |
| 367 | tegra_se_resume(); |
| 368 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 369 | /* |
Varun Wadekar | 4edc17c | 2017-11-20 17:14:47 -0800 | [diff] [blame] | 370 | * Program XUSB STREAMIDs |
| 371 | * ====================== |
| 372 | * T19x XUSB has support for XUSB virtualization. It will |
| 373 | * have one physical function (PF) and four Virtual functions |
| 374 | * (VF) |
| 375 | * |
| 376 | * There were below two SIDs for XUSB until T186. |
| 377 | * 1) #define TEGRA_SID_XUSB_HOST 0x1bU |
| 378 | * 2) #define TEGRA_SID_XUSB_DEV 0x1cU |
| 379 | * |
| 380 | * We have below four new SIDs added for VF(s) |
| 381 | * 3) #define TEGRA_SID_XUSB_VF0 0x5dU |
| 382 | * 4) #define TEGRA_SID_XUSB_VF1 0x5eU |
| 383 | * 5) #define TEGRA_SID_XUSB_VF2 0x5fU |
| 384 | * 6) #define TEGRA_SID_XUSB_VF3 0x60U |
| 385 | * |
| 386 | * When virtualization is enabled then we have to disable SID |
| 387 | * override and program above SIDs in below newly added SID |
| 388 | * registers in XUSB PADCTL MMIO space. These registers are |
| 389 | * TZ protected and so need to be done in ATF. |
| 390 | * |
| 391 | * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) |
| 392 | * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) |
| 393 | * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) |
| 394 | * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) |
| 395 | * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) |
| 396 | * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) |
| 397 | * |
| 398 | * This change disables SID override and programs XUSB SIDs |
| 399 | * in above registers to support both virtualization and |
| 400 | * non-virtualization platforms |
| 401 | */ |
Varun Wadekar | a2eb663 | 2018-03-23 10:44:40 -0700 | [diff] [blame] | 402 | if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { |
| 403 | |
| 404 | mmio_write_32(TEGRA_XUSB_PADCTL_BASE + |
| 405 | XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); |
| 406 | mmio_write_32(TEGRA_XUSB_PADCTL_BASE + |
| 407 | XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); |
| 408 | mmio_write_32(TEGRA_XUSB_PADCTL_BASE + |
| 409 | XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); |
| 410 | mmio_write_32(TEGRA_XUSB_PADCTL_BASE + |
| 411 | XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); |
| 412 | mmio_write_32(TEGRA_XUSB_PADCTL_BASE + |
| 413 | XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); |
| 414 | mmio_write_32(TEGRA_XUSB_PADCTL_BASE + |
| 415 | XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); |
| 416 | } |
Varun Wadekar | 4edc17c | 2017-11-20 17:14:47 -0800 | [diff] [blame] | 417 | |
| 418 | /* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 419 | * Reset power state info for the last core doing SC7 |
| 420 | * entry and exit, we set deepest power state as CC7 |
| 421 | * and SC7 for SC7 entry which may not be requested by |
| 422 | * non-secure SW which controls idle states. |
| 423 | */ |
| 424 | } |
| 425 | |
| 426 | return PSCI_E_SUCCESS; |
| 427 | } |
| 428 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 429 | int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 430 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 431 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 432 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 433 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 434 | (void)target_state; |
| 435 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 436 | /* Disable Denver's DCO operations */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 437 | if (impl == DENVER_IMPL) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 438 | denver_disable_dco(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 439 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 440 | |
| 441 | /* Turn off CPU */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 442 | ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, |
| 443 | (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 444 | assert(ret == 0); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 445 | |
| 446 | return PSCI_E_SUCCESS; |
| 447 | } |
| 448 | |
| 449 | __dead2 void tegra_soc_prepare_system_off(void) |
| 450 | { |
| 451 | /* System power off */ |
Vignesh Radhakrishnan | 2aaa41c | 2017-06-14 09:59:27 -0700 | [diff] [blame] | 452 | mce_system_shutdown(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 453 | |
| 454 | wfi(); |
| 455 | |
| 456 | /* wait for the system to power down */ |
| 457 | for (;;) { |
| 458 | ; |
| 459 | } |
| 460 | } |
| 461 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 462 | int32_t tegra_soc_prepare_system_reset(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 463 | { |
Vignesh Radhakrishnan | 2aaa41c | 2017-06-14 09:59:27 -0700 | [diff] [blame] | 464 | /* System reboot */ |
| 465 | mce_system_reboot(); |
| 466 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 467 | return PSCI_E_SUCCESS; |
| 468 | } |