Tegra194: drivers: SE and RNG1/PKA1 context save support
This patch adds the driver, to implement the programming sequence to
save/restore hardware context, during System Suspend/Resume.
Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 0932061..51c3e95 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -5,21 +5,24 @@
*/
#include <arch.h>
-#include <arch_helpers.h>
#include <assert.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include <arch_helpers.h>
#include <common/bl_common.h>
-#include <context.h>
-#include <lib/el3_runtime/context_mgmt.h>
#include <common/debug.h>
+#include <context.h>
#include <denver.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/psci/psci.h>
#include <mce.h>
#include <plat/common/platform.h>
-#include <lib/psci/psci.h>
+#include <se.h>
#include <smmu.h>
-#include <string.h>
-#include <tegra_private.h>
#include <t194_nvg.h>
-#include <stdbool.h>
+#include <tegra_platform.h>
+#include <tegra_private.h>
extern void tegra_secure_entrypoint(void);
@@ -39,10 +42,7 @@
#define TEGRA186_WAKE_TIME_SHIFT 4U
/* default core wake mask for CPU_SUSPEND */
#define TEGRA194_CORE_WAKE_MASK 0x180cU
-/* context size to save during system suspend */
-#define TEGRA186_SE_CONTEXT_SIZE 3U
-static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
static struct t19x_psci_percpu_data {
uint32_t wake_time;
} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
@@ -134,14 +134,6 @@
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
- /* save SE registers */
- se_regs[0] = mmio_read_32(TEGRA_SE0_BASE +
- SE_MUTEX_WATCHDOG_NS_LIMIT);
- se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE +
- RNG_MUTEX_WATCHDOG_NS_LIMIT);
- se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE +
- PKA_MUTEX_WATCHDOG_NS_LIMIT);
-
/* save 'Secure Boot' Processor Feature Config Register */
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
@@ -157,6 +149,15 @@
tegra_smmu_save_context(0);
#endif
+ /*
+ * Suspend SE, RNG1 and PKA1 only on silcon and fpga,
+ * since VDK does not support atomic se ctx save
+ */
+ if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+ ret = tegra_se_suspend();
+ assert(ret == 0);
+ }
+
if (!tegra_fake_system_suspend) {
/* Prepare for system suspend */
@@ -345,18 +346,12 @@
* context if we are.
*/
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
-
- mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
- se_regs[0]);
- mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,
- se_regs[1]);
- mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT,
- se_regs[2]);
-
/* Init SMMU */
-
tegra_smmu_init();
+ /* Resume SE, RNG1 and PKA1 */
+ tegra_se_resume();
+
/*
* Reset power state info for the last core doing SC7
* entry and exit, we set deepest power state as CC7