Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <common/bl_common.h> |
| 11 | #include <context.h> |
| 12 | #include <lib/el3_runtime/context_mgmt.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <denver.h> |
| 15 | #include <mce.h> |
| 16 | #include <plat/common/platform.h> |
| 17 | #include <lib/psci/psci.h> |
| 18 | #include <smmu.h> |
| 19 | #include <string.h> |
| 20 | #include <tegra_private.h> |
Tejal Kudav | 153ba22 | 2017-02-14 18:02:04 -0800 | [diff] [blame] | 21 | #include <t194_nvg.h> |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 22 | #include <stdbool.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 23 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 24 | extern void tegra_secure_entrypoint(void); |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 25 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 26 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
| 27 | extern void tegra186_cpu_reset_handler(void); |
| 28 | extern uint32_t __tegra186_cpu_reset_handler_data, |
| 29 | __tegra186_cpu_reset_handler_end; |
| 30 | |
| 31 | /* TZDRAM offset for saving SMMU context */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 32 | #define TEGRA186_SMMU_CTX_OFFSET 16U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 33 | #endif |
| 34 | |
| 35 | /* state id mask */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 36 | #define TEGRA186_STATE_ID_MASK 0xFU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 37 | /* constants to get power state's wake time */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 38 | #define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U |
| 39 | #define TEGRA186_WAKE_TIME_SHIFT 4U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 40 | /* default core wake mask for CPU_SUSPEND */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 41 | #define TEGRA194_CORE_WAKE_MASK 0x180cU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 42 | /* context size to save during system suspend */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 43 | #define TEGRA186_SE_CONTEXT_SIZE 3U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 44 | |
| 45 | static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 46 | static struct t19x_psci_percpu_data { |
| 47 | uint32_t wake_time; |
| 48 | } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 49 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 50 | /* |
| 51 | * tegra_fake_system_suspend acts as a boolean var controlling whether |
| 52 | * we are going to take fake system suspend code or normal system suspend code |
| 53 | * path. This variable is set inside the sip call handlers, when the kernel |
| 54 | * requests an SIP call to set the suspend debug flags. |
| 55 | */ |
| 56 | bool tegra_fake_system_suspend; |
| 57 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 58 | int32_t tegra_soc_validate_power_state(uint32_t power_state, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 59 | psci_power_state_t *req_state) |
| 60 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 61 | uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & |
| 62 | TEGRA186_STATE_ID_MASK; |
| 63 | uint32_t cpu = plat_my_core_pos(); |
| 64 | int32_t ret = PSCI_E_SUCCESS; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 65 | |
| 66 | /* save the core wake time (in TSC ticks)*/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 67 | t19x_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 68 | << TEGRA186_WAKE_TIME_SHIFT; |
| 69 | |
| 70 | /* |
| 71 | * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that |
| 72 | * the correct value is read in tegra_soc_pwr_domain_suspend(), which |
| 73 | * is called with caches disabled. It is possible to read a stale value |
| 74 | * from DRAM in that function, because the L2 cache is not flushed |
| 75 | * unless the cluster is entering CC6/CC7. |
| 76 | */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 77 | clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], |
| 78 | sizeof(t19x_percpu_data[cpu])); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 79 | |
| 80 | /* Sanity check the requested state id */ |
| 81 | switch (state_id) { |
| 82 | case PSTATE_ID_CORE_IDLE: |
| 83 | case PSTATE_ID_CORE_POWERDN: |
| 84 | |
| 85 | /* Core powerdown request */ |
| 86 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
| 87 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
| 88 | |
| 89 | break; |
| 90 | |
| 91 | default: |
| 92 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 93 | ret = PSCI_E_INVALID_PARAMS; |
| 94 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 95 | } |
| 96 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 97 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 98 | } |
| 99 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 100 | int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 101 | { |
| 102 | const plat_local_state_t *pwr_domain_state; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 103 | uint8_t stateid_afflvl0, stateid_afflvl2; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 104 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
| 105 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 106 | uint64_t smmu_ctx_base; |
| 107 | #endif |
| 108 | uint32_t val; |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 109 | mce_cstate_info_t sc7_cstate_info = { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 110 | .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, |
| 111 | .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, |
| 112 | .system_state_force = 1U, |
| 113 | .update_wake_mask = 1U, |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 114 | }; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 115 | uint32_t cpu = plat_my_core_pos(); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 116 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 117 | |
| 118 | /* get the state ID */ |
| 119 | pwr_domain_state = target_state->pwr_domain_state; |
| 120 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
| 121 | TEGRA186_STATE_ID_MASK; |
| 122 | stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
| 123 | TEGRA186_STATE_ID_MASK; |
| 124 | |
| 125 | if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || |
| 126 | (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { |
| 127 | |
| 128 | /* Enter CPU idle/powerdown */ |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 129 | val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 130 | (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; |
| 131 | ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 132 | percpu_data[cpu].wake_time, 0); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 133 | assert(ret == 0); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 134 | |
| 135 | } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 136 | |
| 137 | /* save SE registers */ |
| 138 | se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + |
| 139 | SE_MUTEX_WATCHDOG_NS_LIMIT); |
| 140 | se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + |
| 141 | RNG_MUTEX_WATCHDOG_NS_LIMIT); |
| 142 | se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + |
| 143 | PKA_MUTEX_WATCHDOG_NS_LIMIT); |
| 144 | |
| 145 | /* save 'Secure Boot' Processor Feature Config Register */ |
| 146 | val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); |
| 147 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); |
| 148 | |
| 149 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
| 150 | /* save SMMU context */ |
| 151 | smmu_ctx_base = params_from_bl2->tzdram_base + |
| 152 | ((uintptr_t)&__tegra186_cpu_reset_handler_data - |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 153 | (uintptr_t)&tegra186_cpu_reset_handler) + |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 154 | TEGRA186_SMMU_CTX_OFFSET; |
| 155 | tegra_smmu_save_context((uintptr_t)smmu_ctx_base); |
| 156 | #else |
| 157 | tegra_smmu_save_context(0); |
| 158 | #endif |
| 159 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 160 | if (!tegra_fake_system_suspend) { |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 161 | |
| 162 | /* Prepare for system suspend */ |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 163 | mce_update_cstate_info(&sc7_cstate_info); |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 164 | |
| 165 | do { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 166 | val = (uint32_t)mce_command_handler( |
| 167 | (uint32_t)MCE_CMD_IS_SC7_ALLOWED, |
| 168 | (uint32_t)TEGRA_NVG_CORE_C7, |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 169 | MCE_CORE_SLEEP_TIME_INFINITE, |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 170 | 0U); |
| 171 | } while (val == 0U); |
Tejal Kudav | 153ba22 | 2017-02-14 18:02:04 -0800 | [diff] [blame] | 172 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 173 | /* Instruct the MCE to enter system suspend state */ |
| 174 | ret = mce_command_handler( |
| 175 | (uint64_t)MCE_CMD_ENTER_CSTATE, |
| 176 | (uint64_t)TEGRA_NVG_CORE_C7, |
| 177 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 178 | 0U); |
| 179 | assert(ret == 0); |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 180 | } |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 181 | } else { |
| 182 | ; /* do nothing */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | return PSCI_E_SUCCESS; |
| 186 | } |
| 187 | |
| 188 | /******************************************************************************* |
| 189 | * Platform handler to calculate the proper target power level at the |
| 190 | * specified affinity level |
| 191 | ******************************************************************************/ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 192 | plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 193 | const plat_local_state_t *states, |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 194 | uint32_t ncpu) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 195 | { |
| 196 | plat_local_state_t target = *states; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 197 | int32_t cluster_powerdn = 1; |
| 198 | uint32_t core_pos = (uint32_t)read_mpidr() & MPIDR_CPU_MASK; |
| 199 | uint32_t num_cpus = ncpu, pos = 0; |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 200 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 201 | |
| 202 | /* get the current core's power state */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 203 | target = states[core_pos]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 204 | |
| 205 | /* CPU suspend */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 206 | if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CORE_POWERDN)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 207 | |
| 208 | /* Program default wake mask */ |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 209 | cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; |
| 210 | cstate_info.update_wake_mask = 1; |
| 211 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | /* CPU off */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 215 | if ((lvl == MPIDR_AFFLVL1) && (target == PLAT_MAX_OFF_STATE)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 216 | |
| 217 | /* find out the number of ON cpus in the cluster */ |
| 218 | do { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 219 | target = states[pos]; |
| 220 | if (target != PLAT_MAX_OFF_STATE) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 221 | cluster_powerdn = 0; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 222 | } |
| 223 | --num_cpus; |
| 224 | pos++; |
| 225 | } while (num_cpus != 0U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 226 | |
| 227 | /* Enable cluster powerdn from last CPU in the cluster */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 228 | if (cluster_powerdn != 0) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 229 | |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 230 | /* Enable CC6 */ |
| 231 | /* todo */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 232 | |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 233 | /* If cluster group needs to be railgated, request CG7 */ |
| 234 | /* todo */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 235 | |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 236 | /* Turn off wake mask */ |
| 237 | cstate_info.update_wake_mask = 1U; |
| 238 | mce_update_cstate_info(&cstate_info); |
| 239 | |
| 240 | } else { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 241 | /* Turn off wake_mask */ |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 242 | cstate_info.update_wake_mask = 1U; |
| 243 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 244 | } |
| 245 | } |
| 246 | |
| 247 | /* System Suspend */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 248 | if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 249 | return PSTATE_ID_SOC_POWERDN; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 250 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 251 | |
| 252 | /* default state */ |
| 253 | return PSCI_LOCAL_STATE_RUN; |
| 254 | } |
| 255 | |
| 256 | #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 257 | int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 258 | { |
| 259 | const plat_local_state_t *pwr_domain_state = |
| 260 | target_state->pwr_domain_state; |
| 261 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 262 | uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 263 | TEGRA186_STATE_ID_MASK; |
Steven Kao | 55c2ce7 | 2016-12-23 15:51:32 +0800 | [diff] [blame] | 264 | uint64_t val; |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 265 | u_register_t ns_sctlr_el1; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 266 | |
| 267 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 268 | /* |
| 269 | * The TZRAM loses power when we enter system suspend. To |
| 270 | * allow graceful exit from system suspend, we need to copy |
| 271 | * BL3-1 over to TZDRAM. |
| 272 | */ |
| 273 | val = params_from_bl2->tzdram_base + |
| 274 | ((uintptr_t)&__tegra186_cpu_reset_handler_end - |
| 275 | (uintptr_t)tegra186_cpu_reset_handler); |
| 276 | memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, |
| 277 | (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 278 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 279 | /* |
| 280 | * In fake suspend mode, ensure that the loopback procedure |
| 281 | * towards system suspend exit is started, instead of calling |
| 282 | * WFI. This is done by disabling both MMU's of EL1 & El3 |
| 283 | * and calling tegra_secure_entrypoint(). |
| 284 | */ |
| 285 | if (tegra_fake_system_suspend) { |
| 286 | |
| 287 | /* |
| 288 | * Disable EL1's MMU. |
| 289 | */ |
| 290 | ns_sctlr_el1 = read_sctlr_el1(); |
| 291 | ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT)); |
| 292 | write_sctlr_el1(ns_sctlr_el1); |
| 293 | |
| 294 | /* |
| 295 | * Disable MMU to power up the CPU in a "clean" |
| 296 | * state |
| 297 | */ |
| 298 | disable_mmu_el3(); |
| 299 | tegra_secure_entrypoint(); |
| 300 | panic(); |
| 301 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | return PSCI_E_SUCCESS; |
| 305 | } |
| 306 | #endif |
| 307 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 308 | int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 309 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 310 | uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; |
| 311 | uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 312 | MPIDR_AFFINITY_BITS; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 313 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 314 | |
Varun Wadekar | a4e0a81 | 2017-10-17 10:53:33 -0700 | [diff] [blame^] | 315 | if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 316 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); |
| 317 | return PSCI_E_NOT_PRESENT; |
| 318 | } |
| 319 | |
| 320 | /* construct the target CPU # */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 321 | target_cpu += (target_cluster << 1U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 322 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 323 | ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); |
| 324 | if (ret < 0) { |
| 325 | return PSCI_E_DENIED; |
| 326 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 327 | |
| 328 | return PSCI_E_SUCCESS; |
| 329 | } |
| 330 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 331 | int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 332 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 333 | uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 334 | |
| 335 | /* |
| 336 | * Reset power state info for CPUs when onlining, we set |
| 337 | * deepest power when offlining a core but that may not be |
| 338 | * requested by non-secure sw which controls idle states. It |
| 339 | * will re-init this info from non-secure software when the |
| 340 | * core come online. |
| 341 | */ |
| 342 | |
| 343 | /* |
| 344 | * Check if we are exiting from deep sleep and restore SE |
| 345 | * context if we are. |
| 346 | */ |
| 347 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 348 | |
| 349 | mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, |
| 350 | se_regs[0]); |
| 351 | mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, |
| 352 | se_regs[1]); |
| 353 | mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, |
| 354 | se_regs[2]); |
| 355 | |
| 356 | /* Init SMMU */ |
| 357 | |
Vignesh Radhakrishnan | 978887f | 2017-07-11 15:16:08 -0700 | [diff] [blame] | 358 | tegra_smmu_init(); |
| 359 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 360 | /* |
| 361 | * Reset power state info for the last core doing SC7 |
| 362 | * entry and exit, we set deepest power state as CC7 |
| 363 | * and SC7 for SC7 entry which may not be requested by |
| 364 | * non-secure SW which controls idle states. |
| 365 | */ |
| 366 | } |
| 367 | |
| 368 | return PSCI_E_SUCCESS; |
| 369 | } |
| 370 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 371 | int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 372 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 373 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 374 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 375 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 376 | (void)target_state; |
| 377 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 378 | /* Disable Denver's DCO operations */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 379 | if (impl == DENVER_IMPL) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 380 | denver_disable_dco(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 381 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 382 | |
| 383 | /* Turn off CPU */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 384 | ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, |
| 385 | (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 386 | assert(ret == 0); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 387 | |
| 388 | return PSCI_E_SUCCESS; |
| 389 | } |
| 390 | |
| 391 | __dead2 void tegra_soc_prepare_system_off(void) |
| 392 | { |
| 393 | /* System power off */ |
| 394 | |
| 395 | /* SC8 */ |
| 396 | |
| 397 | wfi(); |
| 398 | |
| 399 | /* wait for the system to power down */ |
| 400 | for (;;) { |
| 401 | ; |
| 402 | } |
| 403 | } |
| 404 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 405 | int32_t tegra_soc_prepare_system_reset(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 406 | { |
| 407 | return PSCI_E_SUCCESS; |
| 408 | } |