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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewc53ac5e2016-07-20 14:38:36 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_H__
32#define __ARCH_H__
33
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35/*******************************************************************************
36 * MIDR bit definitions
37 ******************************************************************************/
Soby Mathewc704cbc2014-08-14 11:33:56 +010038#define MIDR_IMPL_MASK 0xff
39#define MIDR_IMPL_SHIFT 0x18
Soby Mathew802f8652014-08-14 16:19:29 +010040#define MIDR_VAR_SHIFT 20
Soby Mathewc0884332014-09-22 12:11:36 +010041#define MIDR_VAR_BITS 4
Soby Mathew802f8652014-08-14 16:19:29 +010042#define MIDR_REV_SHIFT 0
Soby Mathewc0884332014-09-22 12:11:36 +010043#define MIDR_REV_BITS 4
Achin Gupta4f6ad662013-10-25 09:08:21 +010044#define MIDR_PN_MASK 0xfff
45#define MIDR_PN_SHIFT 0x4
Achin Gupta4f6ad662013-10-25 09:08:21 +010046
47/*******************************************************************************
48 * MPIDR macros
49 ******************************************************************************/
50#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
51#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
52#define MPIDR_AFFINITY_BITS 8
53#define MPIDR_AFFLVL_MASK 0xff
54#define MPIDR_AFF0_SHIFT 0
55#define MPIDR_AFF1_SHIFT 8
56#define MPIDR_AFF2_SHIFT 16
57#define MPIDR_AFF3_SHIFT 32
58#define MPIDR_AFFINITY_MASK 0xff00ffffff
59#define MPIDR_AFFLVL_SHIFT 3
60#define MPIDR_AFFLVL0 0
61#define MPIDR_AFFLVL1 1
62#define MPIDR_AFFLVL2 2
63#define MPIDR_AFFLVL3 3
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000064#define MPIDR_AFFLVL0_VAL(mpidr) \
65 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
66#define MPIDR_AFFLVL1_VAL(mpidr) \
67 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
68#define MPIDR_AFFLVL2_VAL(mpidr) \
69 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
70#define MPIDR_AFFLVL3_VAL(mpidr) \
71 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000072/*
73 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
74 * add one while using this macro to define array sizes.
75 * TODO: Support only the first 3 affinity levels for now.
76 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010077#define MPIDR_MAX_AFFLVL 2
78
79/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
80#define FIRST_MPIDR 0
81
82/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010083 * Definitions for CPU system register interface to GICv3
84 ******************************************************************************/
85#define ICC_SRE_EL1 S3_0_C12_C12_5
86#define ICC_SRE_EL2 S3_4_C12_C9_5
87#define ICC_SRE_EL3 S3_6_C12_C12_5
88#define ICC_CTLR_EL1 S3_0_C12_C12_4
89#define ICC_CTLR_EL3 S3_6_C12_C12_4
90#define ICC_PMR_EL1 S3_0_C4_C6_0
Achin Gupta92712a52015-09-03 14:18:02 +010091#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
92#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
93#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
94#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
95#define ICC_IAR0_EL1 S3_0_c12_c8_0
96#define ICC_IAR1_EL1 S3_0_c12_c12_0
97#define ICC_EOIR0_EL1 S3_0_c12_c8_1
98#define ICC_EOIR1_EL1 S3_0_c12_c12_1
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010099
100/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000101 * Generic timer memory mapped registers & offsets
102 ******************************************************************************/
103#define CNTCR_OFF 0x000
104#define CNTFID_OFF 0x020
105
106#define CNTCR_EN (1 << 0)
107#define CNTCR_HDBG (1 << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100108#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000109
110/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 * System register bit definitions
112 ******************************************************************************/
113/* CLIDR definitions */
114#define LOUIS_SHIFT 21
115#define LOC_SHIFT 24
116#define CLIDR_FIELD_WIDTH 3
117
118/* CSSELR definitions */
119#define LEVEL_SHIFT 1
120
121/* D$ set/way op type defines */
122#define DCISW 0x0
123#define DCCISW 0x1
124#define DCCSW 0x2
125
126/* ID_AA64PFR0_EL1 definitions */
127#define ID_AA64PFR0_EL0_SHIFT 0
128#define ID_AA64PFR0_EL1_SHIFT 4
129#define ID_AA64PFR0_EL2_SHIFT 8
130#define ID_AA64PFR0_EL3_SHIFT 12
131#define ID_AA64PFR0_ELX_MASK 0xf
132
Achin Gupta92712a52015-09-03 14:18:02 +0100133#define ID_AA64PFR0_GIC_SHIFT 24
134#define ID_AA64PFR0_GIC_WIDTH 4
135#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1)
136
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137/* ID_PFR1_EL1 definitions */
138#define ID_PFR1_VIRTEXT_SHIFT 12
139#define ID_PFR1_VIRTEXT_MASK 0xf
140#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
141 & ID_PFR1_VIRTEXT_MASK)
142
143/* SCTLR definitions */
144#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
145 (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
146 (1 << 4))
147
148#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
Vikram Kanigiri94efd1f2015-07-22 11:53:52 +0100149 (1 << 20) | (1 << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200150#define SCTLR_AARCH32_EL1_RES1 \
151 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
152 (1 << 3))
153
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154#define SCTLR_M_BIT (1 << 0)
155#define SCTLR_A_BIT (1 << 1)
156#define SCTLR_C_BIT (1 << 2)
157#define SCTLR_SA_BIT (1 << 3)
Soby Mathewa993c422016-09-29 14:15:57 +0100158#define SCTLR_CP15BEN_BIT (1 << 5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159#define SCTLR_I_BIT (1 << 12)
Soby Mathewa993c422016-09-29 14:15:57 +0100160#define SCTLR_NTWI_BIT (1 << 16)
161#define SCTLR_NTWE_BIT (1 << 18)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162#define SCTLR_WXN_BIT (1 << 19)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163#define SCTLR_EE_BIT (1 << 25)
164
Achin Gupta4f6ad662013-10-25 09:08:21 +0100165/* CPACR_El1 definitions */
166#define CPACR_EL1_FPEN(x) (x << 20)
167#define CPACR_EL1_FP_TRAP_EL0 0x1
168#define CPACR_EL1_FP_TRAP_ALL 0x2
169#define CPACR_EL1_FP_TRAP_NONE 0x3
170
171/* SCR definitions */
172#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
173#define SCR_TWE_BIT (1 << 13)
174#define SCR_TWI_BIT (1 << 12)
175#define SCR_ST_BIT (1 << 11)
176#define SCR_RW_BIT (1 << 10)
177#define SCR_SIF_BIT (1 << 9)
178#define SCR_HCE_BIT (1 << 8)
179#define SCR_SMD_BIT (1 << 7)
180#define SCR_EA_BIT (1 << 3)
181#define SCR_FIQ_BIT (1 << 2)
182#define SCR_IRQ_BIT (1 << 1)
183#define SCR_NS_BIT (1 << 0)
Achin Gupta27b895e2014-05-04 18:38:28 +0100184#define SCR_VALID_BIT_MASK 0x2f8f
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185
186/* HCR definitions */
187#define HCR_RW_BIT (1ull << 31)
188#define HCR_AMO_BIT (1 << 5)
189#define HCR_IMO_BIT (1 << 4)
190#define HCR_FMO_BIT (1 << 3)
191
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100192/* ISR definitions */
193#define ISR_A_SHIFT 8
194#define ISR_I_SHIFT 7
195#define ISR_F_SHIFT 6
196
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197/* CNTHCTL_EL2 definitions */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100198#define EVNTEN_BIT (1 << 2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199#define EL1PCEN_BIT (1 << 1)
200#define EL1PCTEN_BIT (1 << 0)
201
202/* CNTKCTL_EL1 definitions */
203#define EL0PTEN_BIT (1 << 9)
204#define EL0VTEN_BIT (1 << 8)
205#define EL0PCTEN_BIT (1 << 0)
206#define EL0VCTEN_BIT (1 << 1)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100207#define EVNTEN_BIT (1 << 2)
208#define EVNTDIR_BIT (1 << 3)
209#define EVNTI_SHIFT 4
210#define EVNTI_MASK 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211
212/* CPTR_EL3 definitions */
Harry Liebel4f603682014-01-14 18:11:48 +0000213#define TCPAC_BIT (1 << 31)
214#define TTA_BIT (1 << 20)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215#define TFP_BIT (1 << 10)
216
217/* CPSR/SPSR definitions */
218#define DAIF_FIQ_BIT (1 << 0)
219#define DAIF_IRQ_BIT (1 << 1)
220#define DAIF_ABT_BIT (1 << 2)
221#define DAIF_DBG_BIT (1 << 3)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100222#define SPSR_DAIF_SHIFT 6
223#define SPSR_DAIF_MASK 0xf
224
225#define SPSR_AIF_SHIFT 6
226#define SPSR_AIF_MASK 0x7
227
228#define SPSR_E_SHIFT 9
229#define SPSR_E_MASK 0x1
230#define SPSR_E_LITTLE 0x0
231#define SPSR_E_BIG 0x1
232
233#define SPSR_T_SHIFT 5
234#define SPSR_T_MASK 0x1
235#define SPSR_T_ARM 0x0
236#define SPSR_T_THUMB 0x1
237
238#define DISABLE_ALL_EXCEPTIONS \
239 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
240
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241
242/*
243 * TCR defintions
244 */
245#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
Lin Ma741a3822014-06-27 16:56:30 -0700246#define TCR_EL1_IPS_SHIFT 32
247#define TCR_EL3_PS_SHIFT 16
248
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100249#define TCR_TxSZ_MIN 16
250#define TCR_TxSZ_MAX 39
251
Lin Ma741a3822014-06-27 16:56:30 -0700252/* (internal) physical address size bits in EL3/EL1 */
253#define TCR_PS_BITS_4GB (0x0)
254#define TCR_PS_BITS_64GB (0x1)
255#define TCR_PS_BITS_1TB (0x2)
256#define TCR_PS_BITS_4TB (0x3)
257#define TCR_PS_BITS_16TB (0x4)
258#define TCR_PS_BITS_256TB (0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259
Lin Ma741a3822014-06-27 16:56:30 -0700260#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL
261#define ADDR_MASK_44_TO_47 0x0000F00000000000UL
262#define ADDR_MASK_42_TO_43 0x00000C0000000000UL
263#define ADDR_MASK_40_TO_41 0x0000030000000000UL
264#define ADDR_MASK_36_TO_39 0x000000F000000000UL
265#define ADDR_MASK_32_TO_35 0x0000000F00000000UL
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266
267#define TCR_RGN_INNER_NC (0x0 << 8)
268#define TCR_RGN_INNER_WBA (0x1 << 8)
269#define TCR_RGN_INNER_WT (0x2 << 8)
270#define TCR_RGN_INNER_WBNA (0x3 << 8)
271
272#define TCR_RGN_OUTER_NC (0x0 << 10)
273#define TCR_RGN_OUTER_WBA (0x1 << 10)
274#define TCR_RGN_OUTER_WT (0x2 << 10)
275#define TCR_RGN_OUTER_WBNA (0x3 << 10)
276
277#define TCR_SH_NON_SHAREABLE (0x0 << 12)
278#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
279#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
280
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100281#define MODE_SP_SHIFT 0x0
282#define MODE_SP_MASK 0x1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283#define MODE_SP_EL0 0x0
284#define MODE_SP_ELX 0x1
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100285
286#define MODE_RW_SHIFT 0x4
287#define MODE_RW_MASK 0x1
288#define MODE_RW_64 0x0
289#define MODE_RW_32 0x1
290
291#define MODE_EL_SHIFT 0x2
292#define MODE_EL_MASK 0x3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293#define MODE_EL3 0x3
294#define MODE_EL2 0x2
295#define MODE_EL1 0x1
296#define MODE_EL0 0x0
297
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100298#define MODE32_SHIFT 0
299#define MODE32_MASK 0xf
300#define MODE32_usr 0x0
301#define MODE32_fiq 0x1
302#define MODE32_irq 0x2
303#define MODE32_svc 0x3
304#define MODE32_mon 0x6
305#define MODE32_abt 0x7
306#define MODE32_hyp 0xa
307#define MODE32_und 0xb
308#define MODE32_sys 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100310#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
311#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
312#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
313#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100314
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100315#define SPSR_64(el, sp, daif) \
316 (MODE_RW_64 << MODE_RW_SHIFT | \
317 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
318 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
319 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
320
321#define SPSR_MODE32(mode, isa, endian, aif) \
322 (MODE_RW_32 << MODE_RW_SHIFT | \
323 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
324 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
325 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
326 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327
Dan Handley0cdebbd2015-03-30 17:15:16 +0100328/*
329 * CTR_EL0 definitions
330 */
331#define CTR_CWG_SHIFT 24
332#define CTR_CWG_MASK 0xf
333#define CTR_ERG_SHIFT 20
334#define CTR_ERG_MASK 0xf
335#define CTR_DMINLINE_SHIFT 16
336#define CTR_DMINLINE_MASK 0xf
337#define CTR_L1IP_SHIFT 14
338#define CTR_L1IP_MASK 0x3
339#define CTR_IMINLINE_SHIFT 0
340#define CTR_IMINLINE_MASK 0xf
341
342#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100343
Achin Gupta405406d2014-05-09 12:00:17 +0100344/* Physical timer control register bit fields shifts and masks */
345#define CNTP_CTL_ENABLE_SHIFT 0
346#define CNTP_CTL_IMASK_SHIFT 1
347#define CNTP_CTL_ISTATUS_SHIFT 2
348
349#define CNTP_CTL_ENABLE_MASK 1
350#define CNTP_CTL_IMASK_MASK 1
351#define CNTP_CTL_ISTATUS_MASK 1
352
353#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \
354 CNTP_CTL_ENABLE_MASK)
355#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \
356 CNTP_CTL_IMASK_MASK)
357#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
358 CNTP_CTL_ISTATUS_MASK)
359
360#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
361#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT)
362
363#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
364#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
365
Achin Gupta4f6ad662013-10-25 09:08:21 +0100366/* Exception Syndrome register bits and bobs */
367#define ESR_EC_SHIFT 26
368#define ESR_EC_MASK 0x3f
369#define ESR_EC_LENGTH 6
370#define EC_UNKNOWN 0x0
371#define EC_WFE_WFI 0x1
372#define EC_AARCH32_CP15_MRC_MCR 0x3
373#define EC_AARCH32_CP15_MRRC_MCRR 0x4
374#define EC_AARCH32_CP14_MRC_MCR 0x5
375#define EC_AARCH32_CP14_LDC_STC 0x6
376#define EC_FP_SIMD 0x7
377#define EC_AARCH32_CP10_MRC 0x8
378#define EC_AARCH32_CP14_MRRC_MCRR 0xc
379#define EC_ILLEGAL 0xe
380#define EC_AARCH32_SVC 0x11
381#define EC_AARCH32_HVC 0x12
382#define EC_AARCH32_SMC 0x13
383#define EC_AARCH64_SVC 0x15
384#define EC_AARCH64_HVC 0x16
385#define EC_AARCH64_SMC 0x17
386#define EC_AARCH64_SYS 0x18
387#define EC_IABORT_LOWER_EL 0x20
388#define EC_IABORT_CUR_EL 0x21
389#define EC_PC_ALIGN 0x22
390#define EC_DABORT_LOWER_EL 0x24
391#define EC_DABORT_CUR_EL 0x25
392#define EC_SP_ALIGN 0x26
393#define EC_AARCH32_FP 0x28
394#define EC_AARCH64_FP 0x2c
395#define EC_SERROR 0x2f
396
397#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
398
Dan Handleyed6ff952014-05-14 17:44:19 +0100399/*******************************************************************************
400 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
401 * system level implementation of the Generic Timer.
402 ******************************************************************************/
403#define CNTNSAR 0x4
404#define CNTNSAR_NS_SHIFT(x) x
405
406#define CNTACR_BASE(x) (0x40 + (x << 2))
407#define CNTACR_RPCT_SHIFT 0x0
408#define CNTACR_RVCT_SHIFT 0x1
409#define CNTACR_RFRQ_SHIFT 0x2
410#define CNTACR_RVOFF_SHIFT 0x3
411#define CNTACR_RWVT_SHIFT 0x4
412#define CNTACR_RWPT_SHIFT 0x5
413
Achin Gupta4f6ad662013-10-25 09:08:21 +0100414#endif /* __ARCH_H__ */