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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Madhukar Pappireddyd7419442020-01-27 15:38:26 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
Dan Handley9df48042015-03-19 18:58:55 +00009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/console.h>
Ambroise Vincent9660dc12019-07-12 13:47:03 +010014#include <lib/debugfs.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/extensions/ras.h>
16#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000018#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000020#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021
Dan Handley9df48042015-03-19 18:58:55 +000022/*
23 * Placeholder variables for copying the arguments that have been passed to
Juan Castillo7d199412015-12-14 09:35:25 +000024 * BL31 from BL2.
Dan Handley9df48042015-03-19 18:58:55 +000025 */
26static entry_point_info_t bl32_image_ep_info;
27static entry_point_info_t bl33_image_ep_info;
28
Soby Mathew7823d9e2018-10-14 08:13:44 +010029#if !RESET_TO_BL31
Soby Mathewaf14b462018-06-01 16:53:38 +010030/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010031 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
Soby Mathewaf14b462018-06-01 16:53:38 +010032 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
33 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010034CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
Soby Mathew7823d9e2018-10-14 08:13:44 +010035#endif
Dan Handley9df48042015-03-19 18:58:55 +000036
37/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000038#pragma weak bl31_early_platform_setup2
Dan Handley9df48042015-03-19 18:58:55 +000039#pragma weak bl31_platform_setup
40#pragma weak bl31_plat_arch_setup
41#pragma weak bl31_plat_get_next_image_ep_info
Dan Handley9df48042015-03-19 18:58:55 +000042
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010043#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
Soby Mathew7823d9e2018-10-14 08:13:44 +010044 BL31_START, \
45 BL31_END - BL31_START, \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010046 MT_MEMORY | MT_RW | MT_SECURE)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010047#if RECLAIM_INIT_CODE
48IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010049IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
David Horstmann8f15ca32020-10-14 15:17:49 +010050IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010051
52#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
53 ~(PAGE_SIZE - 1))
David Horstmann8f15ca32020-10-14 15:17:49 +010054#define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
55 ~(PAGE_SIZE - 1))
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010056
57#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
58 BL_INIT_CODE_BASE, \
59 BL_INIT_CODE_END \
60 - BL_INIT_CODE_BASE, \
61 MT_CODE | MT_SECURE)
62#endif
Dan Handley9df48042015-03-19 18:58:55 +000063
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060064#if SEPARATE_NOBITS_REGION
65#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
66 BL31_NOBITS_BASE, \
67 BL31_NOBITS_LIMIT \
68 - BL31_NOBITS_BASE, \
69 MT_MEMORY | MT_RW | MT_SECURE)
70
71#endif
Dan Handley9df48042015-03-19 18:58:55 +000072/*******************************************************************************
73 * Return a pointer to the 'entry_point_info' structure of the next image for the
Juan Castillo7d199412015-12-14 09:35:25 +000074 * security state specified. BL33 corresponds to the non-secure image type
75 * while BL32 corresponds to the secure image type. A NULL pointer is returned
Dan Handley9df48042015-03-19 18:58:55 +000076 * if the image does not exist.
77 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020078struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
Dan Handley9df48042015-03-19 18:58:55 +000079{
80 entry_point_info_t *next_image_info;
81
82 assert(sec_state_is_valid(type));
83 next_image_info = (type == NON_SECURE)
84 ? &bl33_image_ep_info : &bl32_image_ep_info;
85 /*
86 * None of the images on the ARM development platforms can have 0x0
87 * as the entrypoint
88 */
89 if (next_image_info->pc)
90 return next_image_info;
91 else
92 return NULL;
93}
94
95/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +000096 * Perform any BL31 early platform setup common to ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +000097 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
John Tsichritzisd653d332018-09-14 10:34:57 +010098 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
Dan Handley9df48042015-03-19 18:58:55 +000099 * done before the MMU is initialized so that the memory layout can be used
100 * while creating page tables. BL2 has flushed this information to memory, so
101 * we are guaranteed to pick up good data.
102 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100103void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000104 uintptr_t hw_config, void *plat_params_from_bl2)
Dan Handley9df48042015-03-19 18:58:55 +0000105{
106 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100107 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +0000108
109#if RESET_TO_BL31
Juan Castillo7d199412015-12-14 09:35:25 +0000110 /* There are no parameters from BL2 if BL31 is a reset vector */
Dan Handley9df48042015-03-19 18:58:55 +0000111 assert(from_bl2 == NULL);
112 assert(plat_params_from_bl2 == NULL);
113
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100114# ifdef BL32_BASE
Juan Castillo7d199412015-12-14 09:35:25 +0000115 /* Populate entry point information for BL32 */
Dan Handley9df48042015-03-19 18:58:55 +0000116 SET_PARAM_HEAD(&bl32_image_ep_info,
117 PARAM_EP,
118 VERSION_1,
119 0);
120 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
121 bl32_image_ep_info.pc = BL32_BASE;
122 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
Manish Pandey18a0c3e2020-07-16 00:38:59 +0100123
124#if defined(SPD_spmd)
125 /* SPM (hafnium in secure world) expects SPM Core manifest base address
126 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
127 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
128 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
129 * keep it in the last page.
130 */
131 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
132 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
133#endif
134
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100135# endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000136
Juan Castillo7d199412015-12-14 09:35:25 +0000137 /* Populate entry point information for BL33 */
Dan Handley9df48042015-03-19 18:58:55 +0000138 SET_PARAM_HEAD(&bl33_image_ep_info,
139 PARAM_EP,
140 VERSION_1,
141 0);
142 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000143 * Tell BL31 where the non-trusted software image
Dan Handley9df48042015-03-19 18:58:55 +0000144 * is located and the entry state information
145 */
146 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew4876ae32016-05-09 17:20:10 +0100147
Dan Handley9df48042015-03-19 18:58:55 +0000148 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
149 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
150
Manish Pandey18a0c3e2020-07-16 00:38:59 +0100151#if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33)
152 /*
153 * Hafnium in normal world expects its manifest address in x0, which
154 * is loaded at base of DRAM.
155 */
156 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
157#endif
158
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100159# if ARM_LINUX_KERNEL_AS_BL33
160 /*
161 * According to the file ``Documentation/arm64/booting.txt`` of the
162 * Linux kernel tree, Linux expects the physical address of the device
163 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
164 * must be 0.
165 */
166 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
167 bl33_image_ep_info.args.arg1 = 0U;
168 bl33_image_ep_info.args.arg2 = 0U;
169 bl33_image_ep_info.args.arg3 = 0U;
170# endif
171
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100172#else /* RESET_TO_BL31 */
173
Dan Handley9df48042015-03-19 18:58:55 +0000174 /*
175 * In debug builds, we pass a special value in 'plat_params_from_bl2'
Juan Castillo7d199412015-12-14 09:35:25 +0000176 * to verify platform parameters from BL2 to BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000177 * In release builds, it's not used.
178 */
179 assert(((unsigned long long)plat_params_from_bl2) ==
180 ARM_BL31_PLAT_PARAM_VAL);
181
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100182 /*
183 * Check params passed from BL2 should not be NULL,
184 */
185 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
186 assert(params_from_bl2 != NULL);
187 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
188 assert(params_from_bl2->h.version >= VERSION_2);
189
190 bl_params_node_t *bl_params = params_from_bl2->head;
191
192 /*
193 * Copy BL33 and BL32 (if present), entry point information.
194 * They are stored in Secure RAM, in BL2's address space.
195 */
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100196 while (bl_params != NULL) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100197 if (bl_params->image_id == BL32_IMAGE_ID)
198 bl32_image_ep_info = *bl_params->ep_info;
199
200 if (bl_params->image_id == BL33_IMAGE_ID)
201 bl33_image_ep_info = *bl_params->ep_info;
202
203 bl_params = bl_params->next_params_info;
204 }
205
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100206 if (bl33_image_ep_info.pc == 0U)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100207 panic();
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100208#endif /* RESET_TO_BL31 */
Dan Handley9df48042015-03-19 18:58:55 +0000209}
210
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000211void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
212 u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000213{
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000214 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Dan Handley9df48042015-03-19 18:58:55 +0000215
216 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000217 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +0000218 * No need for locks as no other CPU is active.
219 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000220 plat_arm_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100221
Dan Handley9df48042015-03-19 18:58:55 +0000222 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000223 * Enable Interconnect coherency for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100224 * Earlier bootloader stages might already do this (e.g. Trusted
225 * Firmware's BL1 does it) but we can't assume so. There is no harm in
226 * executing this code twice anyway.
Dan Handley9df48042015-03-19 18:58:55 +0000227 * Platform specific PSCI code will enable coherency for other
228 * clusters.
229 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000230 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000231}
232
233/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000234 * Perform any BL31 platform setup common to ARM standard platforms
Dan Handley9df48042015-03-19 18:58:55 +0000235 ******************************************************************************/
236void arm_bl31_platform_setup(void)
237{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000238 /* Initialize the GIC driver, cpu and distributor interfaces */
239 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +0000240 plat_arm_gic_init();
Dan Handley9df48042015-03-19 18:58:55 +0000241
242#if RESET_TO_BL31
243 /*
244 * Do initial security configuration to allow DRAM/device access
245 * (if earlier BL has not already done so).
246 */
247 plat_arm_security_setup();
248
Roberto Vargas550eb082018-01-05 16:00:05 +0000249#if defined(PLAT_ARM_MEM_PROT_ADDR)
250 arm_nor_psci_do_dyn_mem_protect();
251#endif /* PLAT_ARM_MEM_PROT_ADDR */
252
Dan Handley9df48042015-03-19 18:58:55 +0000253#endif /* RESET_TO_BL31 */
254
255 /* Enable and initialize the System level generic timer */
256 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100257 CNTCR_FCREQ(0U) | CNTCR_EN);
Dan Handley9df48042015-03-19 18:58:55 +0000258
259 /* Allow access to the System counter timer module */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100260 arm_configure_sys_timer();
Dan Handley9df48042015-03-19 18:58:55 +0000261
262 /* Initialize power controller before setting up topology */
263 plat_arm_pwrc_setup();
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000264
265#if RAS_EXTENSION
266 ras_init();
267#endif
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100268
269#if USE_DEBUGFS
270 debugfs_init();
271#endif /* USE_DEBUGFS */
Dan Handley9df48042015-03-19 18:58:55 +0000272}
273
Soby Mathew2fd66be2015-12-09 11:38:43 +0000274/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000275 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
Soby Mathew2fd66be2015-12-09 11:38:43 +0000276 * standard platforms
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100277 * Perform BL31 platform setup
Soby Mathew2fd66be2015-12-09 11:38:43 +0000278 ******************************************************************************/
279void arm_bl31_plat_runtime_setup(void)
280{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100281 console_switch_state(CONSOLE_FLAG_RUNTIME);
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100282
Soby Mathew2fd66be2015-12-09 11:38:43 +0000283 /* Initialize the runtime console */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100284 arm_console_runtime_init();
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000285
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100286#if RECLAIM_INIT_CODE
287 arm_free_init_memory();
288#endif
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000289
290#if PLAT_RO_XLAT_TABLES
291 arm_xlat_make_tables_readonly();
292#endif
Soby Mathew2fd66be2015-12-09 11:38:43 +0000293}
294
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100295#if RECLAIM_INIT_CODE
296/*
David Horstmann8f15ca32020-10-14 15:17:49 +0100297 * Make memory for image boot time code RW to reclaim it as stack for the
298 * secondary cores, or RO where it cannot be reclaimed:
299 *
300 * |-------- INIT SECTION --------|
301 * -----------------------------------------
302 * | CORE 0 | CORE 1 | CORE 2 | EXTRA |
303 * | STACK | STACK | STACK | SPACE |
304 * -----------------------------------------
305 * <-------------------> <------>
306 * MAKE RW AND XN MAKE
307 * FOR STACKS RO AND XN
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100308 */
309void arm_free_init_memory(void)
310{
David Horstmann8f15ca32020-10-14 15:17:49 +0100311 int ret = 0;
312
313 if (BL_STACKS_END < BL_INIT_CODE_END) {
314 /* Reclaim some of the init section as stack if possible. */
315 if (BL_INIT_CODE_BASE < BL_STACKS_END) {
316 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
317 BL_STACKS_END - BL_INIT_CODE_BASE,
318 MT_RW_DATA);
319 }
320 /* Make the rest of the init section read-only. */
321 ret |= xlat_change_mem_attributes(BL_STACKS_END,
322 BL_INIT_CODE_END - BL_STACKS_END,
323 MT_RO_DATA);
324 } else {
325 /* The stacks cover the init section, so reclaim it all. */
326 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100327 BL_INIT_CODE_END - BL_INIT_CODE_BASE,
328 MT_RW_DATA);
David Horstmann8f15ca32020-10-14 15:17:49 +0100329 }
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100330
331 if (ret != 0) {
332 ERROR("Could not reclaim initialization code");
333 panic();
334 }
335}
336#endif
337
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100338void __init bl31_platform_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000339{
340 arm_bl31_platform_setup();
341}
342
Soby Mathew2fd66be2015-12-09 11:38:43 +0000343void bl31_plat_runtime_setup(void)
344{
345 arm_bl31_plat_runtime_setup();
346}
347
Dan Handley9df48042015-03-19 18:58:55 +0000348/*******************************************************************************
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100349 * Perform the very early platform specific architectural setup shared between
350 * ARM standard platforms. This only does basic initialization. Later
351 * architectural setup (bl31_arch_setup()) does not do anything platform
352 * specific.
Dan Handley9df48042015-03-19 18:58:55 +0000353 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100354void __init arm_bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000355{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100356 const mmap_region_t bl_regions[] = {
357 MAP_BL31_TOTAL,
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100358#if RECLAIM_INIT_CODE
359 MAP_BL_INIT_CODE,
360#endif
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600361#if SEPARATE_NOBITS_REGION
362 MAP_BL31_NOBITS,
363#endif
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100364 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100365#if USE_ROMLIB
366 ARM_MAP_ROMLIB_CODE,
367 ARM_MAP_ROMLIB_DATA,
368#endif
Dan Handley9df48042015-03-19 18:58:55 +0000369#if USE_COHERENT_MEM
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100370 ARM_MAP_BL_COHERENT_RAM,
Dan Handley9df48042015-03-19 18:58:55 +0000371#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100372 {0}
373 };
374
Roberto Vargas344ff022018-10-19 16:44:18 +0100375 setup_page_tables(bl_regions, plat_arm_get_mmap());
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100376
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100377 enable_mmu_el3(0);
Roberto Vargase3adc372018-05-23 09:27:06 +0100378
379 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000380}
381
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100382void __init bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000383{
384 arm_bl31_plat_arch_setup();
385}