Blame - common/aarch64/early_exceptions.S - filogic/atf

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Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	1	/*
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	2	* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	3	*
dp-arm	fa3cf0b	2017-05-03 09:38:09 +0100	[diff] [blame]	4	* SPDX-License-Identifier: BSD-3-Clause
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	5	*/
				6
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	7	#include <asm_macros.S>
Yatharth Kochar	6c0566c	2015-10-02 17:56:48 +0100	[diff] [blame]	8	#include <bl_common.h>
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	9
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	10	/* -----------------------------------------------------------------------------
				11	* Very simple stackless exception handlers used by BL2 and BL31 stages.
				12	* BL31 uses them before stacks are setup. BL2 uses them throughout.
				13	* -----------------------------------------------------------------------------
				14	*/
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	15	.globl early_exceptions
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	16
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	17	vector_base early_exceptions
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	18
				19	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	20	* Current EL with SP0 : 0x0 - 0x200
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	21	* -----------------------------------------------------
				22	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	23	vector_entry SynchronousExceptionSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	24	mov x0, #SYNC_EXCEPTION_SP_EL0
				25	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	26	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	27	end_vector_entry SynchronousExceptionSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	28
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	29	vector_entry IrqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	30	mov x0, #IRQ_SP_EL0
				31	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	32	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	33	end_vector_entry IrqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	34
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	35	vector_entry FiqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	36	mov x0, #FIQ_SP_EL0
				37	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	38	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	39	end_vector_entry FiqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	40
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	41	vector_entry SErrorSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	42	mov x0, #SERROR_SP_EL0
				43	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	44	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	45	end_vector_entry SErrorSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	46
				47	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	48	* Current EL with SPx: 0x200 - 0x400
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	49	* -----------------------------------------------------
				50	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	51	vector_entry SynchronousExceptionSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	52	mov x0, #SYNC_EXCEPTION_SP_ELX
				53	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	54	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	55	end_vector_entry SynchronousExceptionSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	56
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	57	vector_entry IrqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	58	mov x0, #IRQ_SP_ELX
				59	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	60	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	61	end_vector_entry IrqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	62
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	63	vector_entry FiqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	64	mov x0, #FIQ_SP_ELX
				65	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	66	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	67	end_vector_entry FiqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	68
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	69	vector_entry SErrorSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	70	mov x0, #SERROR_SP_ELX
				71	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	72	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	73	end_vector_entry SErrorSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	74
				75	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	76	* Lower EL using AArch64 : 0x400 - 0x600
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	77	* -----------------------------------------------------
				78	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	79	vector_entry SynchronousExceptionA64
Sandrine Bailleux	4d05275	2014-03-24 10:24:08 +0000	[diff] [blame]	80	mov x0, #SYNC_EXCEPTION_AARCH64
				81	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	82	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	83	end_vector_entry SynchronousExceptionA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	84
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	85	vector_entry IrqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	86	mov x0, #IRQ_AARCH64
				87	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	88	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	89	end_vector_entry IrqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	90
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	91	vector_entry FiqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	92	mov x0, #FIQ_AARCH64
				93	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	94	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	95	end_vector_entry FiqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	96
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	97	vector_entry SErrorA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	98	mov x0, #SERROR_AARCH64
				99	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	100	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	101	end_vector_entry SErrorA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	102
				103	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	104	* Lower EL using AArch32 : 0x600 - 0x800
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	105	* -----------------------------------------------------
				106	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	107	vector_entry SynchronousExceptionA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	108	mov x0, #SYNC_EXCEPTION_AARCH32
				109	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	110	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	111	end_vector_entry SynchronousExceptionA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	112
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	113	vector_entry IrqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	114	mov x0, #IRQ_AARCH32
				115	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	116	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	117	end_vector_entry IrqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	118
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	119	vector_entry FiqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	120	mov x0, #FIQ_AARCH32
				121	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	122	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	123	end_vector_entry FiqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	124
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	125	vector_entry SErrorA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	126	mov x0, #SERROR_AARCH32
				127	bl plat_report_exception
Jeenu Viswambharan	68aef10	2016-11-30 15:21:11 +0000	[diff] [blame]	128	no_ret plat_panic_handler
Roberto Vargas	95f30ab	2018-04-17 11:31:43 +0100	[diff] [blame]	129	end_vector_entry SErrorA32