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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000031#include <asm_macros.S>
Yatharth Kochar6c0566c2015-10-02 17:56:48 +010032#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010034/* -----------------------------------------------------------------------------
35 * Very simple stackless exception handlers used by BL2 and BL31 stages.
36 * BL31 uses them before stacks are setup. BL2 uses them throughout.
37 * -----------------------------------------------------------------------------
38 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 .globl early_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010041vector_base early_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010042
43 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010044 * Current EL with SP0 : 0x0 - 0x200
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 * -----------------------------------------------------
46 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010047vector_entry SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010048 mov x0, #SYNC_EXCEPTION_SP_EL0
49 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000050 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000051 check_vector_size SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010052
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010053vector_entry IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 mov x0, #IRQ_SP_EL0
55 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000056 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000057 check_vector_size IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010058
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010059vector_entry FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010060 mov x0, #FIQ_SP_EL0
61 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000062 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000063 check_vector_size FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010064
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010065vector_entry SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010066 mov x0, #SERROR_SP_EL0
67 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000068 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000069 check_vector_size SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010070
71 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010072 * Current EL with SPx: 0x200 - 0x400
Achin Gupta4f6ad662013-10-25 09:08:21 +010073 * -----------------------------------------------------
74 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010075vector_entry SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010076 mov x0, #SYNC_EXCEPTION_SP_ELX
77 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000078 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000079 check_vector_size SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010080
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010081vector_entry IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010082 mov x0, #IRQ_SP_ELX
83 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000084 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000085 check_vector_size IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010086
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010087vector_entry FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010088 mov x0, #FIQ_SP_ELX
89 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000090 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000091 check_vector_size FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010092
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010093vector_entry SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010094 mov x0, #SERROR_SP_ELX
95 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000096 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000097 check_vector_size SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010098
99 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100100 * Lower EL using AArch64 : 0x400 - 0x600
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101 * -----------------------------------------------------
102 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100103vector_entry SynchronousExceptionA64
Sandrine Bailleux4d052752014-03-24 10:24:08 +0000104 mov x0, #SYNC_EXCEPTION_AARCH64
105 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000106 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000107 check_vector_size SynchronousExceptionA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000108
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100109vector_entry IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000110 mov x0, #IRQ_AARCH64
111 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000112 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000113 check_vector_size IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000114
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100115vector_entry FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000116 mov x0, #FIQ_AARCH64
117 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000118 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000119 check_vector_size FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000120
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100121vector_entry SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000122 mov x0, #SERROR_AARCH64
123 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000124 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000125 check_vector_size SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000126
127 /* -----------------------------------------------------
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100128 * Lower EL using AArch32 : 0x600 - 0x800
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000129 * -----------------------------------------------------
130 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100131vector_entry SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000132 mov x0, #SYNC_EXCEPTION_AARCH32
133 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000134 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000135 check_vector_size SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000136
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100137vector_entry IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000138 mov x0, #IRQ_AARCH32
139 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000140 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000141 check_vector_size IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000142
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100143vector_entry FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000144 mov x0, #FIQ_AARCH32
145 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000146 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000147 check_vector_size FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000148
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100149vector_entry SErrorA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000150 mov x0, #SERROR_AARCH32
151 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000152 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000153 check_vector_size SErrorA32