Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 7 | #include <arm_config.h> |
| 8 | #include <arm_def.h> |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 9 | #include <assert.h> |
| 10 | #include <cci.h> |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 11 | #include <ccn.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 12 | #include <debug.h> |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 13 | #include <gicv2.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 14 | #include <mmio.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 15 | #include <plat_arm.h> |
| 16 | #include <v2m_def.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 17 | #include "../fvp_def.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 18 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 19 | /* Defines for GIC Driver build time selection */ |
| 20 | #define FVP_GICV2 1 |
| 21 | #define FVP_GICV3 2 |
| 22 | #define FVP_GICV3_LEGACY 3 |
| 23 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 24 | /******************************************************************************* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 25 | * arm_config holds the characteristics of the differences between the three FVP |
| 26 | * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 27 | * at each boot stage by the primary before enabling the MMU (to allow |
| 28 | * interconnect configuration) & used thereafter. Each BL will have its own copy |
| 29 | * to allow independent operation. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | ******************************************************************************/ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 31 | arm_config_t arm_config; |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 32 | |
| 33 | #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ |
| 34 | DEVICE0_SIZE, \ |
| 35 | MT_DEVICE | MT_RW | MT_SECURE) |
| 36 | |
| 37 | #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ |
| 38 | DEVICE1_SIZE, \ |
| 39 | MT_DEVICE | MT_RW | MT_SECURE) |
| 40 | |
Sandrine Bailleux | d9160a5 | 2017-05-26 15:48:10 +0100 | [diff] [blame] | 41 | /* |
| 42 | * Need to be mapped with write permissions in order to set a new non-volatile |
| 43 | * counter value. |
| 44 | */ |
Juan Castillo | 31a68f0 | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 45 | #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ |
| 46 | DEVICE2_SIZE, \ |
Antonio Nino Diaz | 9d602fe | 2016-05-20 14:14:16 +0100 | [diff] [blame] | 47 | MT_DEVICE | MT_RW | MT_SECURE) |
Juan Castillo | 31a68f0 | 2015-04-14 12:49:03 +0100 | [diff] [blame] | 48 | |
| 49 | |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 50 | /* |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 51 | * Table of memory regions for various BL stages to map using the MMU. |
| 52 | * This doesn't include Trusted SRAM as arm_setup_page_tables() already |
| 53 | * takes care of mapping it. |
Sandrine Bailleux | 889ca03 | 2016-06-14 17:01:00 +0100 | [diff] [blame] | 54 | * |
| 55 | * The flash needs to be mapped as writable in order to erase the FIP's Table of |
| 56 | * Contents in case of unrecoverable error (see plat_error_handler()). |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 57 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 58 | #ifdef IMAGE_BL1 |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 59 | const mmap_region_t plat_arm_mmap[] = { |
| 60 | ARM_MAP_SHARED_RAM, |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 61 | V2M_MAP_FLASH0_RW, |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 62 | V2M_MAP_IOFPGA, |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 63 | MAP_DEVICE0, |
| 64 | MAP_DEVICE1, |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 65 | #if TRUSTED_BOARD_BOOT |
Sandrine Bailleux | d9160a5 | 2017-05-26 15:48:10 +0100 | [diff] [blame] | 66 | /* To access the Root of Trust Public Key registers. */ |
| 67 | MAP_DEVICE2, |
| 68 | /* Map DRAM to authenticate NS_BL2U image. */ |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 69 | ARM_MAP_NS_DRAM1, |
| 70 | #endif |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 71 | {0} |
| 72 | }; |
| 73 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 74 | #ifdef IMAGE_BL2 |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 75 | const mmap_region_t plat_arm_mmap[] = { |
| 76 | ARM_MAP_SHARED_RAM, |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 77 | V2M_MAP_FLASH0_RW, |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 78 | V2M_MAP_IOFPGA, |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 79 | MAP_DEVICE0, |
| 80 | MAP_DEVICE1, |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 81 | ARM_MAP_NS_DRAM1, |
| 82 | ARM_MAP_TSP_SEC_MEM, |
Sandrine Bailleux | d9160a5 | 2017-05-26 15:48:10 +0100 | [diff] [blame] | 83 | #if TRUSTED_BOARD_BOOT |
| 84 | /* To access the Root of Trust Public Key registers. */ |
| 85 | MAP_DEVICE2, |
| 86 | #endif |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 87 | #if ARM_BL31_IN_DRAM |
| 88 | ARM_MAP_BL31_SEC_DRAM, |
| 89 | #endif |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 90 | {0} |
| 91 | }; |
| 92 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 93 | #ifdef IMAGE_BL2U |
Yatharth Kochar | 3a11eda | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 94 | const mmap_region_t plat_arm_mmap[] = { |
| 95 | MAP_DEVICE0, |
| 96 | V2M_MAP_IOFPGA, |
| 97 | {0} |
| 98 | }; |
| 99 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 100 | #ifdef IMAGE_BL31 |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 101 | const mmap_region_t plat_arm_mmap[] = { |
| 102 | ARM_MAP_SHARED_RAM, |
| 103 | V2M_MAP_IOFPGA, |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 104 | MAP_DEVICE0, |
| 105 | MAP_DEVICE1, |
| 106 | {0} |
| 107 | }; |
| 108 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 109 | #ifdef IMAGE_BL32 |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 110 | const mmap_region_t plat_arm_mmap[] = { |
Soby Mathew | 0d268dc | 2016-07-11 14:13:56 +0100 | [diff] [blame] | 111 | #ifdef AARCH32 |
| 112 | ARM_MAP_SHARED_RAM, |
| 113 | #endif |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 114 | V2M_MAP_IOFPGA, |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 115 | MAP_DEVICE0, |
| 116 | MAP_DEVICE1, |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 117 | {0} |
| 118 | }; |
Soby Mathew | b08bc04 | 2014-09-03 17:48:44 +0100 | [diff] [blame] | 119 | #endif |
Jon Medhurst | b1eb093 | 2014-02-26 16:27:53 +0000 | [diff] [blame] | 120 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 121 | ARM_CASSERT_MMAP |
Soby Mathew | 13ee968 | 2015-01-22 11:22:22 +0000 | [diff] [blame] | 122 | |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 123 | #if FVP_INTERCONNECT_DRIVER != FVP_CCN |
| 124 | static const int fvp_cci400_map[] = { |
| 125 | PLAT_FVP_CCI400_CLUS0_SL_PORT, |
| 126 | PLAT_FVP_CCI400_CLUS1_SL_PORT, |
| 127 | }; |
| 128 | |
| 129 | static const int fvp_cci5xx_map[] = { |
| 130 | PLAT_FVP_CCI5XX_CLUS0_SL_PORT, |
| 131 | PLAT_FVP_CCI5XX_CLUS1_SL_PORT, |
| 132 | }; |
| 133 | |
| 134 | static unsigned int get_interconnect_master(void) |
| 135 | { |
| 136 | unsigned int master; |
| 137 | u_register_t mpidr; |
| 138 | |
| 139 | mpidr = read_mpidr_el1(); |
| 140 | master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? |
| 141 | MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); |
| 142 | |
| 143 | assert(master < FVP_CLUSTER_COUNT); |
| 144 | return master; |
| 145 | } |
| 146 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 147 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 148 | /******************************************************************************* |
| 149 | * A single boot loader stack is expected to work on both the Foundation FVP |
| 150 | * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The |
| 151 | * SYS_ID register provides a mechanism for detecting the differences between |
| 152 | * these platforms. This information is stored in a per-BL array to allow the |
| 153 | * code to take the correct path.Per BL platform configuration. |
| 154 | ******************************************************************************/ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 155 | void fvp_config_setup(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 156 | { |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 157 | unsigned int rev, hbi, bld, arch, sys_id; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 158 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 159 | sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); |
| 160 | rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; |
| 161 | hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; |
| 162 | bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; |
| 163 | arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 164 | |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 165 | if (arch != ARCH_MODEL) { |
| 166 | ERROR("This firmware is for FVP models\n"); |
James Morrissey | 40a6f64 | 2014-02-10 14:24:36 +0000 | [diff] [blame] | 167 | panic(); |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 168 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | |
| 170 | /* |
| 171 | * The build field in the SYS_ID tells which variant of the GIC |
| 172 | * memory is implemented by the model. |
| 173 | */ |
| 174 | switch (bld) { |
| 175 | case BLD_GIC_VE_MMAP: |
Soby Mathew | cf022c5 | 2016-01-13 17:06:00 +0000 | [diff] [blame] | 176 | ERROR("Legacy Versatile Express memory map for GIC peripheral" |
| 177 | " is not supported\n"); |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 178 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 179 | break; |
| 180 | case BLD_GIC_A53A57_MMAP: |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 181 | break; |
| 182 | default: |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 183 | ERROR("Unsupported board build %x\n", bld); |
| 184 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | /* |
| 188 | * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 |
| 189 | * for the Foundation FVP. |
| 190 | */ |
| 191 | switch (hbi) { |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 192 | case HBI_FOUNDATION_FVP: |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 193 | arm_config.flags = 0; |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 194 | |
| 195 | /* |
| 196 | * Check for supported revisions of Foundation FVP |
| 197 | * Allow future revisions to run but emit warning diagnostic |
| 198 | */ |
| 199 | switch (rev) { |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 200 | case REV_FOUNDATION_FVP_V2_0: |
| 201 | case REV_FOUNDATION_FVP_V2_1: |
| 202 | case REV_FOUNDATION_FVP_v9_1: |
Sandrine Bailleux | 8b33d70 | 2016-09-22 09:46:50 +0100 | [diff] [blame] | 203 | case REV_FOUNDATION_FVP_v9_6: |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 204 | break; |
| 205 | default: |
| 206 | WARN("Unrecognized Foundation FVP revision %x\n", rev); |
| 207 | break; |
| 208 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 209 | break; |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 210 | case HBI_BASE_FVP: |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 211 | arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 212 | |
| 213 | /* |
| 214 | * Check for supported revisions |
| 215 | * Allow future revisions to run but emit warning diagnostic |
| 216 | */ |
| 217 | switch (rev) { |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 218 | case REV_BASE_FVP_V0: |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 219 | arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; |
| 220 | break; |
| 221 | case REV_BASE_FVP_REVC: |
| 222 | arm_config.flags |= (ARM_CONFIG_FVP_SHIFTED_AFF | |
| 223 | ARM_CONFIG_FVP_HAS_SMMUV3 | |
| 224 | ARM_CONFIG_FVP_HAS_CCI5XX); |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 225 | break; |
| 226 | default: |
| 227 | WARN("Unrecognized Base FVP revision %x\n", rev); |
| 228 | break; |
| 229 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 230 | break; |
| 231 | default: |
Andrew Thoelke | 960347d | 2014-06-26 14:27:26 +0100 | [diff] [blame] | 232 | ERROR("Unsupported board HBI number 0x%x\n", hbi); |
| 233 | panic(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 234 | } |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 235 | } |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 236 | |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 237 | |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 238 | void fvp_interconnect_init(void) |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 239 | { |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 240 | #if FVP_INTERCONNECT_DRIVER == FVP_CCN |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 241 | if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { |
| 242 | ERROR("Unrecognized CCN variant detected. Only CCN-502" |
| 243 | " is supported"); |
| 244 | panic(); |
| 245 | } |
| 246 | |
| 247 | plat_arm_interconnect_init(); |
| 248 | #else |
| 249 | uintptr_t cci_base = 0; |
| 250 | const int *cci_map = 0; |
| 251 | unsigned int map_size = 0; |
| 252 | |
| 253 | if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | |
| 254 | ARM_CONFIG_FVP_HAS_CCI5XX))) { |
| 255 | return; |
| 256 | } |
| 257 | |
| 258 | /* Initialize the right interconnect */ |
| 259 | if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { |
| 260 | cci_base = PLAT_FVP_CCI5XX_BASE; |
| 261 | cci_map = fvp_cci5xx_map; |
| 262 | map_size = ARRAY_SIZE(fvp_cci5xx_map); |
| 263 | } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { |
| 264 | cci_base = PLAT_FVP_CCI400_BASE; |
| 265 | cci_map = fvp_cci400_map; |
| 266 | map_size = ARRAY_SIZE(fvp_cci400_map); |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 267 | } |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 268 | |
| 269 | assert(cci_base); |
| 270 | assert(cci_map); |
| 271 | cci_init(cci_base, cci_map, map_size); |
| 272 | #endif |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 273 | } |
| 274 | |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 275 | void fvp_interconnect_enable(void) |
Dan Handley | be234f9 | 2014-08-04 16:11:15 +0100 | [diff] [blame] | 276 | { |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 277 | #if FVP_INTERCONNECT_DRIVER == FVP_CCN |
| 278 | plat_arm_interconnect_enter_coherency(); |
| 279 | #else |
| 280 | unsigned int master; |
| 281 | |
| 282 | if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | |
| 283 | ARM_CONFIG_FVP_HAS_CCI5XX)) { |
| 284 | master = get_interconnect_master(); |
| 285 | cci_enable_snoop_dvm_reqs(master); |
| 286 | } |
| 287 | #endif |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 288 | } |
| 289 | |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 290 | void fvp_interconnect_disable(void) |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 291 | { |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 292 | #if FVP_INTERCONNECT_DRIVER == FVP_CCN |
| 293 | plat_arm_interconnect_exit_coherency(); |
| 294 | #else |
| 295 | unsigned int master; |
| 296 | |
| 297 | if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | |
| 298 | ARM_CONFIG_FVP_HAS_CCI5XX)) { |
| 299 | master = get_interconnect_master(); |
| 300 | cci_disable_snoop_dvm_reqs(master); |
| 301 | } |
| 302 | #endif |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 303 | } |