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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
10#include <context.h>
11#include <context_mgmt.h>
Varun Wadekara2c6be62016-08-01 22:16:21 -070012#include <console.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053013#include <debug.h>
14#include <memctrl.h>
15#include <mmio.h>
16#include <platform.h>
17#include <platform_def.h>
18#include <pmc.h>
19#include <psci.h>
20#include <tegra_def.h>
21#include <tegra_private.h>
22
23extern uint64_t tegra_bl31_phys_base;
Varun Wadekara78bb1b2015-08-07 10:03:00 +053024extern uint64_t tegra_sec_entry_point;
Varun Wadekara2c6be62016-08-01 22:16:21 -070025extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053026
27/*
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080028 * tegra_fake_system_suspend acts as a boolean var controlling whether
29 * we are going to take fake system suspend code or normal system suspend code
30 * path. This variable is set inside the sip call handlers,when the kernel
31 * requests a SIP call to set the suspend debug flags.
32 */
33uint8_t tegra_fake_system_suspend;
34
35/*
Varun Wadekarb316e242015-05-19 16:48:04 +053036 * The following platform setup functions are weakly defined. They
37 * provide typical implementations that will be overridden by a SoC.
38 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +053039#pragma weak tegra_soc_pwr_domain_suspend
40#pragma weak tegra_soc_pwr_domain_on
41#pragma weak tegra_soc_pwr_domain_off
42#pragma weak tegra_soc_pwr_domain_on_finish
Varun Wadekard22429d2016-03-18 14:35:28 -070043#pragma weak tegra_soc_pwr_domain_power_down_wfi
Varun Wadekar8b82fae2015-11-09 17:39:28 -080044#pragma weak tegra_soc_prepare_system_reset
Varun Wadekare5caeed2016-01-07 14:04:21 -080045#pragma weak tegra_soc_prepare_system_off
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070046#pragma weak tegra_soc_get_target_pwr_state
Varun Wadekarb316e242015-05-19 16:48:04 +053047
Varun Wadekara78bb1b2015-08-07 10:03:00 +053048int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053049{
50 return PSCI_E_NOT_SUPPORTED;
51}
52
Varun Wadekara78bb1b2015-08-07 10:03:00 +053053int tegra_soc_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +053054{
55 return PSCI_E_SUCCESS;
56}
57
Varun Wadekara78bb1b2015-08-07 10:03:00 +053058int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053059{
60 return PSCI_E_SUCCESS;
61}
62
Varun Wadekara78bb1b2015-08-07 10:03:00 +053063int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053064{
65 return PSCI_E_SUCCESS;
66}
67
Varun Wadekard22429d2016-03-18 14:35:28 -070068int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
69{
70 return PSCI_E_SUCCESS;
71}
72
Varun Wadekar8b82fae2015-11-09 17:39:28 -080073int tegra_soc_prepare_system_reset(void)
74{
75 return PSCI_E_SUCCESS;
76}
77
Varun Wadekare5caeed2016-01-07 14:04:21 -080078__dead2 void tegra_soc_prepare_system_off(void)
79{
80 ERROR("Tegra System Off: operation not handled.\n");
81 panic();
82}
83
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070084plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
85 const plat_local_state_t *states,
86 unsigned int ncpu)
87{
Varun Wadekar14eaede2016-09-01 14:51:59 -070088 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070089
90 assert(ncpu);
91
92 do {
93 temp = *states++;
Varun Wadekar14eaede2016-09-01 14:51:59 -070094 if ((temp < target))
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070095 target = temp;
96 } while (--ncpu);
97
98 return target;
99}
100
Varun Wadekarb316e242015-05-19 16:48:04 +0530101/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530102 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
103 * call to get the `power_state` parameter. This allows the platform to encode
104 * the appropriate State-ID field within the `power_state` parameter which can
105 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
106******************************************************************************/
107void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530108{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700109 /* all affinities use system suspend state id */
110 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
111 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
Varun Wadekarb316e242015-05-19 16:48:04 +0530112}
113
114/*******************************************************************************
115 * Handler called when an affinity instance is about to enter standby.
116 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530117void tegra_cpu_standby(plat_local_state_t cpu_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530118{
119 /*
120 * Enter standby state
121 * dsb is good practice before using wfi to enter low power states
122 */
123 dsb();
124 wfi();
125}
126
127/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530128 * Handler called when an affinity instance is about to be turned on. The
129 * level and mpidr determine the affinity instance.
130 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530131int tegra_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +0530132{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530133 return tegra_soc_pwr_domain_on(mpidr);
Varun Wadekarb316e242015-05-19 16:48:04 +0530134}
135
136/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530137 * Handler called when a power domain is about to be turned off. The
138 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530139 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530140void tegra_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530141{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530142 tegra_soc_pwr_domain_off(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530143}
144
145/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700146 * Handler called when a power domain is about to be suspended. The
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530147 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530148 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530149void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530150{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530151 tegra_soc_pwr_domain_suspend(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530152
Varun Wadekara2c6be62016-08-01 22:16:21 -0700153 /* Disable console if we are entering deep sleep. */
154 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
155 PSTATE_ID_SOC_POWERDN)
156 console_uninit();
157
Varun Wadekarb316e242015-05-19 16:48:04 +0530158 /* disable GICC */
159 tegra_gic_cpuif_deactivate();
160}
161
162/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700163 * Handler called at the end of the power domain suspend sequence. The
164 * target_state encodes the power state that each level should transition to.
165 ******************************************************************************/
166__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
167 *target_state)
168{
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800169 uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
170 uint64_t rmr_el3 = 0;
171
Varun Wadekard22429d2016-03-18 14:35:28 -0700172 /* call the chip's power down handler */
173 tegra_soc_pwr_domain_power_down_wfi(target_state);
174
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800175 /*
176 * If we are in fake system suspend mode, ensure we start doing
177 * procedures that help in looping back towards system suspend exit
178 * instead of calling WFI by requesting a warm reset.
179 * Else, just call WFI to enter low power state.
180 */
181 if ((tegra_fake_system_suspend != 0U) &&
182 (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) {
183
184 /* warm reboot */
185 rmr_el3 = read_rmr_el3();
186 write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU);
187
188 } else {
189 /* enter power down state */
190 wfi();
191 }
Varun Wadekard22429d2016-03-18 14:35:28 -0700192
193 /* we can never reach here */
Varun Wadekard22429d2016-03-18 14:35:28 -0700194 panic();
195}
196
197/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530198 * Handler called when a power domain has just been powered on after
199 * being turned off earlier. The target_state encodes the low power state that
200 * each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530201 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530202void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530203{
204 plat_params_from_bl2_t *plat_params;
205
206 /*
Varun Wadekarb316e242015-05-19 16:48:04 +0530207 * Initialize the GIC cpu and distributor interfaces
208 */
Varun Wadekarb7b45752015-12-28 14:55:41 -0800209 plat_gic_setup();
Varun Wadekarb316e242015-05-19 16:48:04 +0530210
211 /*
212 * Check if we are exiting from deep sleep.
213 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530214 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
215 PSTATE_ID_SOC_POWERDN) {
Varun Wadekarb316e242015-05-19 16:48:04 +0530216
Varun Wadekara2c6be62016-08-01 22:16:21 -0700217 /* Initialize the runtime console */
Damon Duan777baa52016-11-07 19:37:50 +0800218 if (tegra_console_base != (uint64_t)0) {
219 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
220 TEGRA_CONSOLE_BAUDRATE);
221 }
Varun Wadekara2c6be62016-08-01 22:16:21 -0700222
Varun Wadekarb316e242015-05-19 16:48:04 +0530223 /*
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800224 * Restore Memory Controller settings as it loses state
225 * during system suspend.
Varun Wadekarb316e242015-05-19 16:48:04 +0530226 */
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800227 tegra_memctrl_restore_settings();
Varun Wadekarb316e242015-05-19 16:48:04 +0530228
229 /*
230 * Security configuration to allow DRAM/device access.
231 */
232 plat_params = bl31_get_plat_params();
Varun Wadekar6bb62462015-10-06 12:49:31 +0530233 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
Varun Wadekarb316e242015-05-19 16:48:04 +0530234 plat_params->tzdram_size);
Varun Wadekard5f578a2016-06-01 19:34:37 -0700235
236 /*
237 * Set up the TZRAM memory aperture to allow only secure world
238 * access
239 */
240 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
Varun Wadekarb316e242015-05-19 16:48:04 +0530241 }
242
243 /*
244 * Reset hardware settings.
245 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530246 tegra_soc_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530247}
248
249/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530250 * Handler called when a power domain has just been powered on after
251 * having been suspended earlier. The target_state encodes the low power state
252 * that each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530253 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530254void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530255{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530256 tegra_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530257}
258
259/*******************************************************************************
260 * Handler called when the system wants to be powered off
261 ******************************************************************************/
262__dead2 void tegra_system_off(void)
263{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800264 INFO("Powering down system...\n");
265
266 tegra_soc_prepare_system_off();
Varun Wadekarb316e242015-05-19 16:48:04 +0530267}
268
269/*******************************************************************************
270 * Handler called when the system wants to be restarted.
271 ******************************************************************************/
272__dead2 void tegra_system_reset(void)
273{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800274 INFO("Restarting system...\n");
275
Varun Wadekar8b82fae2015-11-09 17:39:28 -0800276 /* per-SoC system reset handler */
277 tegra_soc_prepare_system_reset();
278
Varun Wadekarb316e242015-05-19 16:48:04 +0530279 /*
280 * Program the PMC in order to restart the system.
281 */
282 tegra_pmc_system_reset();
283}
284
285/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530286 * Handler called to check the validity of the power state parameter.
287 ******************************************************************************/
288int32_t tegra_validate_power_state(unsigned int power_state,
289 psci_power_state_t *req_state)
290{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530291 assert(req_state);
292
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530293 return tegra_soc_validate_power_state(power_state, req_state);
294}
295
296/*******************************************************************************
297 * Platform handler called to check the validity of the non secure entrypoint.
298 ******************************************************************************/
299int tegra_validate_ns_entrypoint(uintptr_t entrypoint)
300{
301 /*
302 * Check if the non secure entrypoint lies within the non
303 * secure DRAM.
304 */
305 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END))
306 return PSCI_E_SUCCESS;
307
308 return PSCI_E_INVALID_ADDRESS;
309}
310
311/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530312 * Export the platform handlers to enable psci to invoke them
313 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530314static const plat_psci_ops_t tegra_plat_psci_ops = {
315 .cpu_standby = tegra_cpu_standby,
316 .pwr_domain_on = tegra_pwr_domain_on,
317 .pwr_domain_off = tegra_pwr_domain_off,
318 .pwr_domain_suspend = tegra_pwr_domain_suspend,
319 .pwr_domain_on_finish = tegra_pwr_domain_on_finish,
320 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
Varun Wadekard22429d2016-03-18 14:35:28 -0700321 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530322 .system_off = tegra_system_off,
323 .system_reset = tegra_system_reset,
324 .validate_power_state = tegra_validate_power_state,
325 .validate_ns_entrypoint = tegra_validate_ns_entrypoint,
326 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state,
Varun Wadekarb316e242015-05-19 16:48:04 +0530327};
328
329/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530330 * Export the platform specific power ops and initialize Power Controller
Varun Wadekarb316e242015-05-19 16:48:04 +0530331 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530332int plat_setup_psci_ops(uintptr_t sec_entrypoint,
333 const plat_psci_ops_t **psci_ops)
Varun Wadekarb316e242015-05-19 16:48:04 +0530334{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530335 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } };
336
337 /*
338 * Flush entrypoint variable to PoC since it will be
339 * accessed after a reset with the caches turned off.
340 */
341 tegra_sec_entry_point = sec_entrypoint;
342 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t));
343
Varun Wadekarb316e242015-05-19 16:48:04 +0530344 /*
345 * Reset hardware settings.
346 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530347 tegra_soc_pwr_domain_on_finish(&target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530348
349 /*
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530350 * Initialize PSCI ops struct
Varun Wadekarb316e242015-05-19 16:48:04 +0530351 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530352 *psci_ops = &tegra_plat_psci_ops;
Varun Wadekarb316e242015-05-19 16:48:04 +0530353
354 return 0;
355}
Varun Wadekar24975392016-05-05 14:13:30 -0700356
357/*******************************************************************************
358 * Platform handler to calculate the proper target power level at the
359 * specified affinity level
360 ******************************************************************************/
361plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
362 const plat_local_state_t *states,
363 unsigned int ncpu)
364{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700365 return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
Varun Wadekar24975392016-05-05 14:13:30 -0700366}