Tegra: allow individual SoCs to restore their settings
This patch uses the Memory controller driver's handler to restore
its settings and moves the other chip specific code to their own
'pwr_domain_on_finish' handlers.
Change-Id: I3c9d23bdab9e2e3c05034ff6812cf941ccd7a75e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 683af28..64405fb 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -168,14 +168,10 @@
PSTATE_ID_SOC_POWERDN) {
/*
- * Lock scratch registers which hold the CPU vectors.
- */
- tegra_pmc_lock_cpu_vectors();
-
- /*
- * SMMU configuration.
+ * Restore Memory Controller settings as it loses state
+ * during system suspend.
*/
- tegra_memctrl_setup();
+ tegra_memctrl_restore_settings();
/*
* Security configuration to allow DRAM/device access.