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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar6077dce2016-01-27 11:31:06 -08002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <bl_common.h>
34#include <context.h>
35#include <context_mgmt.h>
Varun Wadekara2c6be62016-08-01 22:16:21 -070036#include <console.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053037#include <debug.h>
38#include <memctrl.h>
39#include <mmio.h>
40#include <platform.h>
41#include <platform_def.h>
42#include <pmc.h>
43#include <psci.h>
44#include <tegra_def.h>
45#include <tegra_private.h>
46
47extern uint64_t tegra_bl31_phys_base;
Varun Wadekara78bb1b2015-08-07 10:03:00 +053048extern uint64_t tegra_sec_entry_point;
Varun Wadekara2c6be62016-08-01 22:16:21 -070049extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053050
51/*
52 * The following platform setup functions are weakly defined. They
53 * provide typical implementations that will be overridden by a SoC.
54 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +053055#pragma weak tegra_soc_pwr_domain_suspend
56#pragma weak tegra_soc_pwr_domain_on
57#pragma weak tegra_soc_pwr_domain_off
58#pragma weak tegra_soc_pwr_domain_on_finish
Varun Wadekard22429d2016-03-18 14:35:28 -070059#pragma weak tegra_soc_pwr_domain_power_down_wfi
Varun Wadekar8b82fae2015-11-09 17:39:28 -080060#pragma weak tegra_soc_prepare_system_reset
Varun Wadekare5caeed2016-01-07 14:04:21 -080061#pragma weak tegra_soc_prepare_system_off
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070062#pragma weak tegra_soc_get_target_pwr_state
Varun Wadekarb316e242015-05-19 16:48:04 +053063
Varun Wadekara78bb1b2015-08-07 10:03:00 +053064int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053065{
66 return PSCI_E_NOT_SUPPORTED;
67}
68
Varun Wadekara78bb1b2015-08-07 10:03:00 +053069int tegra_soc_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +053070{
71 return PSCI_E_SUCCESS;
72}
73
Varun Wadekara78bb1b2015-08-07 10:03:00 +053074int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053075{
76 return PSCI_E_SUCCESS;
77}
78
Varun Wadekara78bb1b2015-08-07 10:03:00 +053079int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053080{
81 return PSCI_E_SUCCESS;
82}
83
Varun Wadekard22429d2016-03-18 14:35:28 -070084int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
85{
86 return PSCI_E_SUCCESS;
87}
88
Varun Wadekar8b82fae2015-11-09 17:39:28 -080089int tegra_soc_prepare_system_reset(void)
90{
91 return PSCI_E_SUCCESS;
92}
93
Varun Wadekare5caeed2016-01-07 14:04:21 -080094__dead2 void tegra_soc_prepare_system_off(void)
95{
96 ERROR("Tegra System Off: operation not handled.\n");
97 panic();
98}
99
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700100plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
101 const plat_local_state_t *states,
102 unsigned int ncpu)
103{
Varun Wadekar14eaede2016-09-01 14:51:59 -0700104 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700105
106 assert(ncpu);
107
108 do {
109 temp = *states++;
Varun Wadekar14eaede2016-09-01 14:51:59 -0700110 if ((temp < target))
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700111 target = temp;
112 } while (--ncpu);
113
114 return target;
115}
116
Varun Wadekarb316e242015-05-19 16:48:04 +0530117/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530118 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
119 * call to get the `power_state` parameter. This allows the platform to encode
120 * the appropriate State-ID field within the `power_state` parameter which can
121 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
122******************************************************************************/
123void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530124{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700125 /* all affinities use system suspend state id */
126 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
127 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
Varun Wadekarb316e242015-05-19 16:48:04 +0530128}
129
130/*******************************************************************************
131 * Handler called when an affinity instance is about to enter standby.
132 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530133void tegra_cpu_standby(plat_local_state_t cpu_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530134{
135 /*
136 * Enter standby state
137 * dsb is good practice before using wfi to enter low power states
138 */
139 dsb();
140 wfi();
141}
142
143/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530144 * Handler called when an affinity instance is about to be turned on. The
145 * level and mpidr determine the affinity instance.
146 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530147int tegra_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +0530148{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530149 return tegra_soc_pwr_domain_on(mpidr);
Varun Wadekarb316e242015-05-19 16:48:04 +0530150}
151
152/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530153 * Handler called when a power domain is about to be turned off. The
154 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530155 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530156void tegra_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530157{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530158 tegra_soc_pwr_domain_off(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530159}
160
161/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700162 * Handler called when a power domain is about to be suspended. The
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530163 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530164 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530165void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530166{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530167 tegra_soc_pwr_domain_suspend(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530168
Varun Wadekara2c6be62016-08-01 22:16:21 -0700169 /* Disable console if we are entering deep sleep. */
170 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
171 PSTATE_ID_SOC_POWERDN)
172 console_uninit();
173
Varun Wadekarb316e242015-05-19 16:48:04 +0530174 /* disable GICC */
175 tegra_gic_cpuif_deactivate();
176}
177
178/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700179 * Handler called at the end of the power domain suspend sequence. The
180 * target_state encodes the power state that each level should transition to.
181 ******************************************************************************/
182__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
183 *target_state)
184{
185 /* call the chip's power down handler */
186 tegra_soc_pwr_domain_power_down_wfi(target_state);
187
188 /* enter power down state */
189 wfi();
190
191 /* we can never reach here */
192 ERROR("%s: operation not handled.\n", __func__);
193 panic();
194}
195
196/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530197 * Handler called when a power domain has just been powered on after
198 * being turned off earlier. The target_state encodes the low power state that
199 * each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530200 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530201void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530202{
203 plat_params_from_bl2_t *plat_params;
204
205 /*
Varun Wadekarb316e242015-05-19 16:48:04 +0530206 * Initialize the GIC cpu and distributor interfaces
207 */
Varun Wadekarb7b45752015-12-28 14:55:41 -0800208 plat_gic_setup();
Varun Wadekarb316e242015-05-19 16:48:04 +0530209
210 /*
211 * Check if we are exiting from deep sleep.
212 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530213 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
214 PSTATE_ID_SOC_POWERDN) {
Varun Wadekarb316e242015-05-19 16:48:04 +0530215
Varun Wadekara2c6be62016-08-01 22:16:21 -0700216 /* Initialize the runtime console */
217 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
218 TEGRA_CONSOLE_BAUDRATE);
219
Varun Wadekarb316e242015-05-19 16:48:04 +0530220 /*
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800221 * Restore Memory Controller settings as it loses state
222 * during system suspend.
Varun Wadekarb316e242015-05-19 16:48:04 +0530223 */
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800224 tegra_memctrl_restore_settings();
Varun Wadekarb316e242015-05-19 16:48:04 +0530225
226 /*
227 * Security configuration to allow DRAM/device access.
228 */
229 plat_params = bl31_get_plat_params();
Varun Wadekar6bb62462015-10-06 12:49:31 +0530230 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
Varun Wadekarb316e242015-05-19 16:48:04 +0530231 plat_params->tzdram_size);
Varun Wadekard5f578a2016-06-01 19:34:37 -0700232
233 /*
234 * Set up the TZRAM memory aperture to allow only secure world
235 * access
236 */
237 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
Varun Wadekarb316e242015-05-19 16:48:04 +0530238 }
239
240 /*
241 * Reset hardware settings.
242 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530243 tegra_soc_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530244}
245
246/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530247 * Handler called when a power domain has just been powered on after
248 * having been suspended earlier. The target_state encodes the low power state
249 * that each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530250 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530251void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530252{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530253 tegra_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530254}
255
256/*******************************************************************************
257 * Handler called when the system wants to be powered off
258 ******************************************************************************/
259__dead2 void tegra_system_off(void)
260{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800261 INFO("Powering down system...\n");
262
263 tegra_soc_prepare_system_off();
Varun Wadekarb316e242015-05-19 16:48:04 +0530264}
265
266/*******************************************************************************
267 * Handler called when the system wants to be restarted.
268 ******************************************************************************/
269__dead2 void tegra_system_reset(void)
270{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800271 INFO("Restarting system...\n");
272
Varun Wadekar8b82fae2015-11-09 17:39:28 -0800273 /* per-SoC system reset handler */
274 tegra_soc_prepare_system_reset();
275
Varun Wadekarb316e242015-05-19 16:48:04 +0530276 /*
277 * Program the PMC in order to restart the system.
278 */
279 tegra_pmc_system_reset();
280}
281
282/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530283 * Handler called to check the validity of the power state parameter.
284 ******************************************************************************/
285int32_t tegra_validate_power_state(unsigned int power_state,
286 psci_power_state_t *req_state)
287{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530288 assert(req_state);
289
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530290 return tegra_soc_validate_power_state(power_state, req_state);
291}
292
293/*******************************************************************************
294 * Platform handler called to check the validity of the non secure entrypoint.
295 ******************************************************************************/
296int tegra_validate_ns_entrypoint(uintptr_t entrypoint)
297{
298 /*
299 * Check if the non secure entrypoint lies within the non
300 * secure DRAM.
301 */
302 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END))
303 return PSCI_E_SUCCESS;
304
305 return PSCI_E_INVALID_ADDRESS;
306}
307
308/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530309 * Export the platform handlers to enable psci to invoke them
310 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530311static const plat_psci_ops_t tegra_plat_psci_ops = {
312 .cpu_standby = tegra_cpu_standby,
313 .pwr_domain_on = tegra_pwr_domain_on,
314 .pwr_domain_off = tegra_pwr_domain_off,
315 .pwr_domain_suspend = tegra_pwr_domain_suspend,
316 .pwr_domain_on_finish = tegra_pwr_domain_on_finish,
317 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
Varun Wadekard22429d2016-03-18 14:35:28 -0700318 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530319 .system_off = tegra_system_off,
320 .system_reset = tegra_system_reset,
321 .validate_power_state = tegra_validate_power_state,
322 .validate_ns_entrypoint = tegra_validate_ns_entrypoint,
323 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state,
Varun Wadekarb316e242015-05-19 16:48:04 +0530324};
325
326/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530327 * Export the platform specific power ops and initialize Power Controller
Varun Wadekarb316e242015-05-19 16:48:04 +0530328 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530329int plat_setup_psci_ops(uintptr_t sec_entrypoint,
330 const plat_psci_ops_t **psci_ops)
Varun Wadekarb316e242015-05-19 16:48:04 +0530331{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530332 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } };
333
334 /*
335 * Flush entrypoint variable to PoC since it will be
336 * accessed after a reset with the caches turned off.
337 */
338 tegra_sec_entry_point = sec_entrypoint;
339 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t));
340
Varun Wadekarb316e242015-05-19 16:48:04 +0530341 /*
342 * Reset hardware settings.
343 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530344 tegra_soc_pwr_domain_on_finish(&target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530345
346 /*
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530347 * Initialize PSCI ops struct
Varun Wadekarb316e242015-05-19 16:48:04 +0530348 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530349 *psci_ops = &tegra_plat_psci_ops;
Varun Wadekarb316e242015-05-19 16:48:04 +0530350
351 return 0;
352}
Varun Wadekar24975392016-05-05 14:13:30 -0700353
354/*******************************************************************************
355 * Platform handler to calculate the proper target power level at the
356 * specified affinity level
357 ******************************************************************************/
358plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
359 const plat_local_state_t *states,
360 unsigned int ncpu)
361{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700362 return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
Varun Wadekar24975392016-05-05 14:13:30 -0700363}