blob: 3ad3dd40ef12132ff7493fc097a970e3e5d814f6 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewa0fedc42016-06-16 14:52:04 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000034#include <debug.h>
35#include <platform.h>
Soby Mathewd0194872016-04-29 19:01:30 +010036#include <smcc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010037#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010038#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
40/*******************************************************************************
41 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
42 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010043int psci_cpu_on(u_register_t target_cpu,
44 uintptr_t entrypoint,
45 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010046
47{
48 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000049 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010050
51 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010052 rc = psci_validate_mpidr(target_cpu);
53 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010054 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010055
Soby Mathewf1f97a12015-07-15 12:13:26 +010056 /* Validate the entry point and get the entry_point_info */
57 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000058 if (rc != PSCI_E_SUCCESS)
59 return rc;
60
Soby Mathew8595b872015-01-06 15:36:38 +000061 /*
Soby Mathew981487a2015-07-13 14:10:57 +010062 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000063 * levels need to be turned on
64 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010065 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010066}
67
68unsigned int psci_version(void)
69{
70 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
71}
72
73int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010074 uintptr_t entrypoint,
75 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076{
77 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010078 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000079 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010080 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
81 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010082
Soby Mathew981487a2015-07-13 14:10:57 +010083 /* Validate the power_state parameter */
84 rc = psci_validate_power_state(power_state, &state_info);
85 if (rc != PSCI_E_SUCCESS) {
86 assert(rc == PSCI_E_INVALID_PARAMS);
87 return rc;
88 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010089
Soby Mathew981487a2015-07-13 14:10:57 +010090 /*
91 * Get the value of the state type bit from the power state parameter.
92 */
93 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010094
Soby Mathew981487a2015-07-13 14:10:57 +010095 /* Sanity check the requested suspend levels */
Soby Mathew24ab34f2016-05-03 17:11:42 +010096 assert(psci_validate_suspend_req(&state_info, is_power_down_state)
Soby Mathew981487a2015-07-13 14:10:57 +010097 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010098
Soby Mathew981487a2015-07-13 14:10:57 +010099 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
Sandrine Bailleuxf9f3bbf2016-06-22 16:35:01 +0100100 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
101 ERROR("Invalid target power level for suspend operation\n");
102 panic();
103 }
Soby Mathew981487a2015-07-13 14:10:57 +0100104
105 /* Fast path for CPU standby.*/
106 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
107 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +0100108 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +0100109
Soby Mathew981487a2015-07-13 14:10:57 +0100110 /*
111 * Set the state of the CPU power domain to the platform
112 * specific retention state and enter the standby state.
113 */
114 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
115 psci_set_cpu_local_state(cpu_pd_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100116
117#if ENABLE_PSCI_STAT
118 /*
119 * Capture time-stamp before CPU standby
120 * No cache maintenance is needed as caches
121 * are ON through out the CPU standby operation.
122 */
123 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
124 PMF_NO_CACHE_MAINT);
125#endif
126
Soby Mathew981487a2015-07-13 14:10:57 +0100127 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100128
Soby Mathew981487a2015-07-13 14:10:57 +0100129 /* Upon exit from standby, set the state back to RUN. */
130 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100131
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100132#if ENABLE_PSCI_STAT
133 /* Capture time-stamp after CPU standby */
134 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
135 PMF_NO_CACHE_MAINT);
136
137 /* Update PSCI stats */
138 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info,
139 PMF_NO_CACHE_MAINT);
140#endif
141
Soby Mathew74e52a72014-10-02 16:56:51 +0100142 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000143 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
Achin Gupta42c52802014-05-09 19:32:25 +0100145 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100146 * If a power down state has been requested, we need to verify entry
147 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000148 */
Soby Mathew981487a2015-07-13 14:10:57 +0100149 if (is_power_down_state) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100150 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100151 if (rc != PSCI_E_SUCCESS)
152 return rc;
153 }
Soby Mathewf5121572014-09-30 11:19:51 +0100154
Soby Mathew8595b872015-01-06 15:36:38 +0000155 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100156 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100157 * enter the final wfi which will power down this CPU. This function
158 * might return if the power down was abandoned for any reason, e.g.
159 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100160 */
Soby Mathew981487a2015-07-13 14:10:57 +0100161 psci_cpu_suspend_start(&ep,
162 target_pwrlvl,
163 &state_info,
164 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100165
Soby Mathew74e52a72014-10-02 16:56:51 +0100166 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167}
168
Soby Mathew011ca182015-07-29 17:05:03 +0100169
170int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000171{
172 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100173 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000174 entry_point_info_t ep;
175
Soby Mathew96168382014-12-17 14:47:57 +0000176 /* Check if the current CPU is the last ON CPU in the system */
177 if (!psci_is_last_on_cpu())
178 return PSCI_E_DENIED;
179
Soby Mathewf1f97a12015-07-15 12:13:26 +0100180 /* Validate the entry point and get the entry_point_info */
181 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000182 if (rc != PSCI_E_SUCCESS)
183 return rc;
184
Soby Mathew981487a2015-07-13 14:10:57 +0100185 /* Query the psci_power_state for system suspend */
186 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000187
Soby Mathew981487a2015-07-13 14:10:57 +0100188 /* Ensure that the psci_power_state makes sense */
189 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
190 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
191 == PSCI_E_SUCCESS);
192 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000193
194 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100195 * Do what is needed to enter the system suspend state. This function
196 * might return if the power down was abandoned for any reason, e.g.
197 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000198 */
Soby Mathew981487a2015-07-13 14:10:57 +0100199 psci_cpu_suspend_start(&ep,
200 PLAT_MAX_PWR_LVL,
201 &state_info,
202 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000203
Soby Mathew96168382014-12-17 14:47:57 +0000204 return PSCI_E_SUCCESS;
205}
206
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207int psci_cpu_off(void)
208{
209 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100210 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100213 * Do what is needed to power off this CPU and possible higher power
214 * levels if it able to do so. Upon success, enter the final wfi
215 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216 */
Soby Mathew981487a2015-07-13 14:10:57 +0100217 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218
Achin Gupta3140a9e2013-12-02 16:23:12 +0000219 /*
220 * The only error cpu_off can return is E_DENIED. So check if that's
221 * indeed the case.
222 */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100223 assert(rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224
225 return rc;
226}
227
Soby Mathew011ca182015-07-29 17:05:03 +0100228int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229 unsigned int lowest_affinity_level)
230{
Soby Mathew981487a2015-07-13 14:10:57 +0100231 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
Soby Mathew981487a2015-07-13 14:10:57 +0100233 /* We dont support level higher than PSCI_CPU_PWR_LVL */
234 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
235 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236
Soby Mathew981487a2015-07-13 14:10:57 +0100237 /* Calculate the cpu index of the target */
238 target_idx = plat_core_pos_by_mpidr(target_affinity);
239 if (target_idx == -1)
240 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000241
Soby Mathew981487a2015-07-13 14:10:57 +0100242 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243}
244
Soby Mathew011ca182015-07-29 17:05:03 +0100245int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246{
Soby Mathew110fe362014-10-23 10:35:34 +0100247 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100248 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100249
250 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
251 if (rc != PSCI_TOS_UP_MIG_CAP)
252 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
253 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
254
255 /*
256 * Migrate should only be invoked on the CPU where
257 * the Secure OS is resident.
258 */
259 if (resident_cpu_mpidr != read_mpidr_el1())
260 return PSCI_E_NOT_PRESENT;
261
262 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100263 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100264 if (rc != PSCI_E_SUCCESS)
265 return PSCI_E_INVALID_PARAMS;
266
267 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
268
269 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
270 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
271
272 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273}
274
Soby Mathew110fe362014-10-23 10:35:34 +0100275int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276{
Soby Mathew011ca182015-07-29 17:05:03 +0100277 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100278
279 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280}
281
Soby Mathew110fe362014-10-23 10:35:34 +0100282long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283{
Soby Mathew011ca182015-07-29 17:05:03 +0100284 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100285 int rc;
286
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100288 * Return value of this depends upon what
289 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100290 */
Soby Mathew110fe362014-10-23 10:35:34 +0100291 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
292 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
293 return PSCI_E_INVALID_PARAMS;
294
295 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100296}
297
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000298int psci_features(unsigned int psci_fid)
299{
Soby Mathew011ca182015-07-29 17:05:03 +0100300 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000301
302 /* Check if it is a 64 bit function */
303 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
304 local_caps &= PSCI_CAP_64BIT_MASK;
305
306 /* Check for invalid fid */
307 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
308 && is_psci_fid(psci_fid)))
309 return PSCI_E_NOT_SUPPORTED;
310
311
312 /* Check if the psci fid is supported or not */
313 if (!(local_caps & define_psci_cap(psci_fid)))
314 return PSCI_E_NOT_SUPPORTED;
315
316 /* Format the feature flags */
317 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
318 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
319 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100320 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000321 */
Soby Mathew981487a2015-07-13 14:10:57 +0100322 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000323 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
324 }
325
326 /* Return 0 for all other fid's */
327 return PSCI_E_SUCCESS;
328}
329
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000330/*******************************************************************************
331 * PSCI top level handler for servicing SMCs.
332 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100333u_register_t psci_smc_handler(uint32_t smc_fid,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100334 u_register_t x1,
335 u_register_t x2,
336 u_register_t x3,
337 u_register_t x4,
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000338 void *cookie,
339 void *handle,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100340 u_register_t flags)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000341{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100342 if (is_caller_secure(flags))
Soby Mathewd0194872016-04-29 19:01:30 +0100343 return SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000344
Soby Mathew61e615b2015-01-15 11:49:49 +0000345 /* Check the fid against the capabilities */
346 if (!(psci_caps & define_psci_cap(smc_fid)))
Soby Mathewd0194872016-04-29 19:01:30 +0100347 return SMC_UNK;
Soby Mathew61e615b2015-01-15 11:49:49 +0000348
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100349 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
350 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000351
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100352 x1 = (uint32_t)x1;
353 x2 = (uint32_t)x2;
354 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000355
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100356 switch (smc_fid) {
357 case PSCI_VERSION:
Soby Mathewd0194872016-04-29 19:01:30 +0100358 return psci_version();
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000359
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100360 case PSCI_CPU_OFF:
Soby Mathewd0194872016-04-29 19:01:30 +0100361 return psci_cpu_off();
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000362
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100363 case PSCI_CPU_SUSPEND_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100364 return psci_cpu_suspend(x1, x2, x3);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000365
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100366 case PSCI_CPU_ON_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100367 return psci_cpu_on(x1, x2, x3);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000368
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100369 case PSCI_AFFINITY_INFO_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100370 return psci_affinity_info(x1, x2);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000371
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100372 case PSCI_MIG_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100373 return psci_migrate(x1);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000374
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100375 case PSCI_MIG_INFO_TYPE:
Soby Mathewd0194872016-04-29 19:01:30 +0100376 return psci_migrate_info_type();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100377
378 case PSCI_MIG_INFO_UP_CPU_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100379 return psci_migrate_info_up_cpu();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100380
Soby Mathew96168382014-12-17 14:47:57 +0000381 case PSCI_SYSTEM_SUSPEND_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100382 return psci_system_suspend(x1, x2);
Soby Mathew96168382014-12-17 14:47:57 +0000383
Juan Castillo4dc4a472014-08-12 11:17:06 +0100384 case PSCI_SYSTEM_OFF:
385 psci_system_off();
386 /* We should never return from psci_system_off() */
387
388 case PSCI_SYSTEM_RESET:
389 psci_system_reset();
390 /* We should never return from psci_system_reset() */
391
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000392 case PSCI_FEATURES:
Soby Mathewd0194872016-04-29 19:01:30 +0100393 return psci_features(x1);
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000394
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100395#if ENABLE_PSCI_STAT
396 case PSCI_STAT_RESIDENCY_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100397 return psci_stat_residency(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100398
399 case PSCI_STAT_COUNT_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100400 return psci_stat_count(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100401#endif
402
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100403 default:
404 break;
405 }
406 } else {
407 /* 64-bit PSCI function */
408
409 switch (smc_fid) {
410 case PSCI_CPU_SUSPEND_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100411 return psci_cpu_suspend(x1, x2, x3);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100412
413 case PSCI_CPU_ON_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100414 return psci_cpu_on(x1, x2, x3);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100415
416 case PSCI_AFFINITY_INFO_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100417 return psci_affinity_info(x1, x2);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100418
419 case PSCI_MIG_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100420 return psci_migrate(x1);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100421
422 case PSCI_MIG_INFO_UP_CPU_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100423 return psci_migrate_info_up_cpu();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100424
Soby Mathew96168382014-12-17 14:47:57 +0000425 case PSCI_SYSTEM_SUSPEND_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100426 return psci_system_suspend(x1, x2);
Soby Mathew96168382014-12-17 14:47:57 +0000427
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100428#if ENABLE_PSCI_STAT
429 case PSCI_STAT_RESIDENCY_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100430 return psci_stat_residency(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100431
432 case PSCI_STAT_COUNT_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100433 return psci_stat_count(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100434#endif
435
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100436 default:
437 break;
438 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000439 }
440
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100441 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
Soby Mathewd0194872016-04-29 19:01:30 +0100442 return SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000443}