Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. |
Michal Simek | d4ff272 | 2023-04-20 08:01:03 +0200 | [diff] [blame] | 3 | * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * Top-level SMC handler for ZynqMP power management calls and |
| 10 | * IPI setup functions for communication with PMU. |
| 11 | */ |
| 12 | |
| 13 | #include <errno.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | |
| 15 | #include <common/runtime_svc.h> |
| 16 | #if ZYNQMP_WDT_RESTART |
| 17 | #include <arch_helpers.h> |
| 18 | #include <drivers/arm/gicv2.h> |
| 19 | #include <lib/mmio.h> |
| 20 | #include <lib/spinlock.h> |
| 21 | #include <plat/common/platform.h> |
| 22 | #endif |
| 23 | |
Jolly Shah | 0bfd700 | 2019-01-08 11:10:47 -0800 | [diff] [blame] | 24 | #include <plat_private.h> |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 25 | #include "pm_client.h" |
| 26 | #include "pm_ipi.h" |
Jay Buddhabhatti | 26e138a | 2022-12-21 23:03:35 -0800 | [diff] [blame] | 27 | #include "zynqmp_pm_api_sys.h" |
Jay Buddhabhatti | 5b9f391 | 2023-02-02 22:34:03 -0800 | [diff] [blame] | 28 | #include "zynqmp_pm_defs.h" |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 29 | |
Rajan Vaja | 720fd9d | 2018-10-05 04:42:57 -0700 | [diff] [blame] | 30 | /* pm_up = !0 - UP, pm_up = 0 - DOWN */ |
| 31 | static int32_t pm_up, ipi_irq_flag; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 32 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 33 | #if ZYNQMP_WDT_RESTART |
| 34 | static spinlock_t inc_lock; |
| 35 | static int active_cores = 0; |
| 36 | #endif |
| 37 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 38 | /** |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 39 | * typedef pm_ctx_t - Structure which contains data for power management. |
| 40 | * @api_version: version of PM API, must match with one on PMU side. |
| 41 | * @payload: payload array used to store received. |
| 42 | * data from ipi buffer registers. |
| 43 | * |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 44 | */ |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 45 | typedef struct { |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 46 | uint32_t api_version; |
| 47 | uint32_t payload[PAYLOAD_ARG_CNT]; |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 48 | } pm_ctx_t; |
| 49 | |
| 50 | static pm_ctx_t pm_ctx; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 51 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 52 | #if ZYNQMP_WDT_RESTART |
| 53 | /** |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 54 | * trigger_wdt_restart() - Trigger warm restart event to APU cores. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 55 | * |
| 56 | * This function triggers SGI for all active APU CPUs. SGI handler then |
| 57 | * power down CPU and call system reset. |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 58 | * |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 59 | */ |
| 60 | static void trigger_wdt_restart(void) |
| 61 | { |
| 62 | uint32_t core_count = 0; |
| 63 | uint32_t core_status[3]; |
| 64 | uint32_t target_cpu_list = 0; |
| 65 | int i; |
| 66 | |
| 67 | for (i = 0; i < 4; i++) { |
| 68 | pm_get_node_status(NODE_APU_0 + i, core_status); |
| 69 | if (core_status[0] == 1) { |
| 70 | core_count++; |
| 71 | target_cpu_list |= (1 << i); |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | spin_lock(&inc_lock); |
| 76 | active_cores = core_count; |
| 77 | spin_unlock(&inc_lock); |
| 78 | |
| 79 | INFO("Active Cores: %d\n", active_cores); |
| 80 | |
Siva Durga Prasad Paladugu | 60bfbc9 | 2018-09-24 22:51:49 -0700 | [diff] [blame] | 81 | for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { |
| 82 | if (target_cpu_list & (1 << i)) { |
| 83 | /* trigger SGI to active cores */ |
| 84 | plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); |
| 85 | } |
| 86 | } |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | /** |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 90 | * ttc_fiq_handler() - TTC Handler for timer event. |
| 91 | * @id: number of the highest priority pending interrupt of the type |
| 92 | * that this handler was registered for. |
| 93 | * @flags: security state, bit[0]. |
| 94 | * @handle: pointer to 'cpu_context' structure of the current CPU for the |
| 95 | * security state specified in the 'flags' parameter. |
| 96 | * @cookie: unused. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 97 | * |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 98 | * Function registered as INTR_TYPE_EL3 interrupt handler. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 99 | * |
| 100 | * When WDT event is received in PMU, PMU needs to notify master to do cleanup |
| 101 | * if required. PMU sets up timer and starts timer to overflow in zero time upon |
Prasad Kummari | e078311 | 2023-04-26 11:02:07 +0530 | [diff] [blame] | 102 | * WDT event. TF-A handles this timer event and takes necessary action required |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 103 | * for warm restart. |
| 104 | * |
| 105 | * In presence of non-secure software layers (EL1/2) sets the interrupt |
Elyes Haouas | 2be03c0 | 2023-02-13 09:14:48 +0100 | [diff] [blame] | 106 | * at registered entrance in GIC and informs that PMU responded or demands |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 107 | * action. |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 108 | * |
| 109 | * Return: 0 on success. |
| 110 | * |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 111 | */ |
| 112 | static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, |
Michal Simek | 08341b7 | 2022-03-09 08:53:20 +0100 | [diff] [blame] | 113 | void *cookie) |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 114 | { |
| 115 | INFO("BL31: Got TTC FIQ\n"); |
| 116 | |
Siva Durga Prasad Paladugu | 60bfbc9 | 2018-09-24 22:51:49 -0700 | [diff] [blame] | 117 | plat_ic_end_of_interrupt(id); |
| 118 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 119 | /* Clear TTC interrupt by reading interrupt register */ |
| 120 | mmio_read_32(TTC3_INTR_REGISTER_1); |
| 121 | |
| 122 | /* Disable the timer interrupts */ |
| 123 | mmio_write_32(TTC3_INTR_ENABLE_1, 0); |
| 124 | |
| 125 | trigger_wdt_restart(); |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 130 | /** |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 131 | * zynqmp_sgi7_irq() - Handler for SGI7 IRQ. |
| 132 | * @id: number of the highest priority pending interrupt of the type |
| 133 | * that this handler was registered for. |
| 134 | * @flags: security state, bit[0]. |
| 135 | * @handle: pointer to 'cpu_context' structure of the current CPU for the |
| 136 | * security state specified in the 'flags' parameter. |
| 137 | * @cookie: unused. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 138 | * |
| 139 | * Function registered as INTR_TYPE_EL3 interrupt handler |
| 140 | * |
Prasad Kummari | e078311 | 2023-04-26 11:02:07 +0530 | [diff] [blame] | 141 | * On receiving WDT event from PMU, TF-A generates SGI7 to all running CPUs. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 142 | * In response to SGI7 interrupt, each CPUs do clean up if required and last |
| 143 | * running CPU calls system restart. |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 144 | * |
| 145 | * Return: This function does not return a value and it enters into wfi. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 146 | */ |
| 147 | static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, |
Michal Simek | 08341b7 | 2022-03-09 08:53:20 +0100 | [diff] [blame] | 148 | void *handle, void *cookie) |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 149 | { |
| 150 | int i; |
Will Wong | cc12795 | 2020-11-22 23:45:21 -0800 | [diff] [blame] | 151 | uint32_t value; |
| 152 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 153 | /* enter wfi and stay there */ |
| 154 | INFO("Entering wfi\n"); |
| 155 | |
| 156 | spin_lock(&inc_lock); |
| 157 | active_cores--; |
| 158 | |
| 159 | for (i = 0; i < 4; i++) { |
| 160 | mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, |
| 161 | 0xffffffff); |
| 162 | } |
| 163 | |
Tanmay Shah | 50702ba | 2022-09-13 11:10:08 -0700 | [diff] [blame] | 164 | dsb(); |
| 165 | |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 166 | spin_unlock(&inc_lock); |
| 167 | |
| 168 | if (active_cores == 0) { |
Will Wong | cc12795 | 2020-11-22 23:45:21 -0800 | [diff] [blame] | 169 | pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value); |
| 170 | value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; |
| 171 | pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value); |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | /* enter wfi and stay there */ |
| 175 | while (1) |
| 176 | wfi(); |
| 177 | } |
| 178 | |
| 179 | /** |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 180 | * pm_wdt_restart_setup() - Setup warm restart interrupts. |
| 181 | * |
| 182 | * Return: Returns status, 0 on success or error+reason. |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 183 | * |
| 184 | * This function sets up handler for SGI7 and TTC interrupts |
| 185 | * used for warm restart. |
| 186 | */ |
| 187 | static int pm_wdt_restart_setup(void) |
| 188 | { |
| 189 | int ret; |
| 190 | |
| 191 | /* register IRQ handler for SGI7 */ |
| 192 | ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq); |
| 193 | if (ret) { |
| 194 | WARN("BL31: registering SGI7 interrupt failed\n"); |
| 195 | goto err; |
| 196 | } |
| 197 | |
| 198 | ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler); |
| 199 | if (ret) |
| 200 | WARN("BL31: registering TTC3 interrupt failed\n"); |
| 201 | |
| 202 | err: |
| 203 | return ret; |
| 204 | } |
| 205 | #endif |
| 206 | |
| 207 | /** |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 208 | * pm_setup() - PM service setup. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 209 | * |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 210 | * Return: On success, the initialization function must return 0. |
| 211 | * Any other return value will cause the framework to ignore |
| 212 | * the service. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 213 | * |
| 214 | * Initialization functions for ZynqMP power management for |
| 215 | * communicaton with PMU. |
| 216 | * |
| 217 | * Called from sip_svc_setup initialization function with the |
| 218 | * rt_svc_init signature. |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 219 | * |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 220 | */ |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 221 | int32_t pm_setup(void) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 222 | { |
Naman Patel | 0feb5ea | 2022-11-22 05:01:37 -0800 | [diff] [blame] | 223 | enum pm_ret_status err; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 224 | |
HariBabu Gattem | aa81171 | 2022-10-07 00:07:49 -0700 | [diff] [blame] | 225 | pm_ipi_init(primary_proc); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 226 | |
Naman Patel | 0feb5ea | 2022-11-22 05:01:37 -0800 | [diff] [blame] | 227 | err = pm_get_api_version(&pm_ctx.api_version); |
| 228 | if (err != PM_RET_SUCCESS) { |
| 229 | ERROR("BL31: Failed to read Platform Management API version. " |
| 230 | "Return: %d\n", err); |
| 231 | return -EINVAL; |
| 232 | } |
Rajan Vaja | 720fd9d | 2018-10-05 04:42:57 -0700 | [diff] [blame] | 233 | if (pm_ctx.api_version < PM_VERSION) { |
| 234 | ERROR("BL31: Platform Management API version error. Expected: " |
| 235 | "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR, |
| 236 | PM_VERSION_MINOR, pm_ctx.api_version >> 16, |
Venkatesh Yadav Abbarapu | a2ca35d | 2022-07-04 11:40:27 +0530 | [diff] [blame] | 237 | pm_ctx.api_version & 0xFFFFU); |
Rajan Vaja | 720fd9d | 2018-10-05 04:42:57 -0700 | [diff] [blame] | 238 | return -EINVAL; |
| 239 | } |
| 240 | |
HariBabu Gattem | aa81171 | 2022-10-07 00:07:49 -0700 | [diff] [blame] | 241 | int32_t status = 0, ret = 0; |
Siva Durga Prasad Paladugu | efd431b | 2018-04-30 20:12:12 +0530 | [diff] [blame] | 242 | #if ZYNQMP_WDT_RESTART |
| 243 | status = pm_wdt_restart_setup(); |
| 244 | if (status) |
| 245 | WARN("BL31: warm-restart setup failed\n"); |
| 246 | #endif |
| 247 | |
Wendy Liang | 328105c | 2017-10-03 23:21:11 -0700 | [diff] [blame] | 248 | if (status >= 0) { |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 249 | INFO("BL31: PM Service Init Complete: API v%d.%d\n", |
| 250 | PM_VERSION_MAJOR, PM_VERSION_MINOR); |
Wendy Liang | 328105c | 2017-10-03 23:21:11 -0700 | [diff] [blame] | 251 | ret = 0; |
| 252 | } else { |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 253 | INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); |
Wendy Liang | 328105c | 2017-10-03 23:21:11 -0700 | [diff] [blame] | 254 | ret = status; |
| 255 | } |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 256 | |
Siva Durga Prasad Paladugu | 79f7595 | 2018-04-30 19:39:49 +0530 | [diff] [blame] | 257 | pm_up = !status; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 258 | |
Wendy Liang | 328105c | 2017-10-03 23:21:11 -0700 | [diff] [blame] | 259 | return ret; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | /** |
| 263 | * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 264 | * @smc_fid: Function Identifier. |
| 265 | * @x1: Arguments. |
| 266 | * @x2: Arguments. |
| 267 | * @x3: Arguments. |
| 268 | * @x4: Arguments. |
| 269 | * @cookie: Unused. |
| 270 | * @handle: Pointer to caller's context structure. |
| 271 | * @flags: SECURE_FLAG or NON_SECURE_FLAG. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 272 | * |
| 273 | * Determines that smc_fid is valid and supported PM SMC Function ID from the |
| 274 | * list of pm_api_ids, otherwise completes the request with |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 275 | * the unknown SMC Function ID. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 276 | * |
| 277 | * The SMC calls for PM service are forwarded from SIP Service SMC handler |
Prasad Kummari | 7d0623a | 2023-06-09 14:32:00 +0530 | [diff] [blame^] | 278 | * function with rt_svc_handle signature. |
| 279 | * |
| 280 | * Return: Unused. |
| 281 | * |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 282 | */ |
| 283 | uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, |
Venkatesh Yadav Abbarapu | 0386e65 | 2022-05-24 14:05:57 +0530 | [diff] [blame] | 284 | uint64_t x4, const void *cookie, void *handle, uint64_t flags) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 285 | { |
| 286 | enum pm_ret_status ret; |
Ronak Jain | 52de594 | 2022-01-20 23:11:18 -0800 | [diff] [blame] | 287 | uint32_t payload[PAYLOAD_ARG_CNT]; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 288 | |
Ronak Jain | f841467 | 2022-05-11 02:48:52 -0700 | [diff] [blame] | 289 | uint32_t pm_arg[5]; |
HariBabu Gattem | aa81171 | 2022-10-07 00:07:49 -0700 | [diff] [blame] | 290 | uint32_t result[PAYLOAD_ARG_CNT] = {0}; |
Ronak Jain | 52de594 | 2022-01-20 23:11:18 -0800 | [diff] [blame] | 291 | uint32_t api_id; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 292 | |
| 293 | /* Handle case where PM wasn't initialized properly */ |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 294 | if (pm_up == 0) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 295 | SMC_RET1(handle, SMC_UNK); |
| 296 | |
| 297 | pm_arg[0] = (uint32_t)x1; |
| 298 | pm_arg[1] = (uint32_t)(x1 >> 32); |
| 299 | pm_arg[2] = (uint32_t)x2; |
| 300 | pm_arg[3] = (uint32_t)(x2 >> 32); |
Ronak Jain | 52de594 | 2022-01-20 23:11:18 -0800 | [diff] [blame] | 301 | pm_arg[4] = (uint32_t)x3; |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 302 | |
Ronak Jain | 52de594 | 2022-01-20 23:11:18 -0800 | [diff] [blame] | 303 | api_id = smc_fid & FUNCID_NUM_MASK; |
| 304 | |
| 305 | switch (api_id) { |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 306 | /* PM API Functions */ |
| 307 | case PM_SELF_SUSPEND: |
| 308 | ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], |
| 309 | pm_arg[3]); |
| 310 | SMC_RET1(handle, (uint64_t)ret); |
| 311 | |
| 312 | case PM_REQ_SUSPEND: |
| 313 | ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], |
| 314 | pm_arg[3]); |
| 315 | SMC_RET1(handle, (uint64_t)ret); |
| 316 | |
| 317 | case PM_REQ_WAKEUP: |
Filip Drazic | 78ba145 | 2017-02-07 12:03:57 +0100 | [diff] [blame] | 318 | { |
| 319 | /* Use address flag is encoded in the 1st bit of the low-word */ |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 320 | uint32_t set_addr = pm_arg[1] & 0x1U; |
| 321 | uint64_t address = (uint64_t)pm_arg[2] << 32U; |
Filip Drazic | 78ba145 | 2017-02-07 12:03:57 +0100 | [diff] [blame] | 322 | |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 323 | address |= pm_arg[1] & (~0x1U); |
Filip Drazic | 78ba145 | 2017-02-07 12:03:57 +0100 | [diff] [blame] | 324 | ret = pm_req_wakeup(pm_arg[0], set_addr, address, |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 325 | pm_arg[3]); |
| 326 | SMC_RET1(handle, (uint64_t)ret); |
Filip Drazic | 78ba145 | 2017-02-07 12:03:57 +0100 | [diff] [blame] | 327 | } |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 328 | |
| 329 | case PM_FORCE_POWERDOWN: |
| 330 | ret = pm_force_powerdown(pm_arg[0], pm_arg[1]); |
| 331 | SMC_RET1(handle, (uint64_t)ret); |
| 332 | |
| 333 | case PM_ABORT_SUSPEND: |
| 334 | ret = pm_abort_suspend(pm_arg[0]); |
| 335 | SMC_RET1(handle, (uint64_t)ret); |
| 336 | |
| 337 | case PM_SET_WAKEUP_SOURCE: |
| 338 | ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]); |
| 339 | SMC_RET1(handle, (uint64_t)ret); |
| 340 | |
| 341 | case PM_SYSTEM_SHUTDOWN: |
Soren Brinkmann | 58fbb9b | 2016-09-02 09:50:54 -0700 | [diff] [blame] | 342 | ret = pm_system_shutdown(pm_arg[0], pm_arg[1]); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 343 | SMC_RET1(handle, (uint64_t)ret); |
| 344 | |
| 345 | case PM_REQ_NODE: |
| 346 | ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); |
| 347 | SMC_RET1(handle, (uint64_t)ret); |
| 348 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 349 | case PM_SET_REQUIREMENT: |
| 350 | ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], |
| 351 | pm_arg[3]); |
| 352 | SMC_RET1(handle, (uint64_t)ret); |
| 353 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 354 | case PM_GET_API_VERSION: |
Boyan Karatotev | b3d2b4f | 2022-11-22 12:13:44 +0000 | [diff] [blame] | 355 | if (ipi_irq_flag == 0U) { |
| 356 | /* |
| 357 | * Enable IPI IRQ |
| 358 | * assume the rich OS is OK to handle callback IRQs now. |
| 359 | * Even if we were wrong, it would not enable the IRQ in |
| 360 | * the GIC. |
| 361 | */ |
| 362 | pm_ipi_irq_enable(primary_proc); |
| 363 | ipi_irq_flag = 1U; |
Soren Brinkmann | a1b0a90 | 2016-09-30 11:30:21 -0700 | [diff] [blame] | 364 | } |
Boyan Karatotev | b3d2b4f | 2022-11-22 12:13:44 +0000 | [diff] [blame] | 365 | SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | |
| 366 | ((uint64_t)pm_ctx.api_version << 32)); |
Nava kishore Manne | 68d460c | 2016-08-20 23:18:09 +0530 | [diff] [blame] | 367 | case PM_FPGA_LOAD: |
| 368 | ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); |
| 369 | SMC_RET1(handle, (uint64_t)ret); |
| 370 | |
| 371 | case PM_FPGA_GET_STATUS: |
| 372 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 373 | uint32_t value = 0U; |
Nava kishore Manne | 68d460c | 2016-08-20 23:18:09 +0530 | [diff] [blame] | 374 | |
| 375 | ret = pm_fpga_get_status(&value); |
| 376 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); |
| 377 | } |
| 378 | |
Siva Durga Prasad Paladugu | de93d98 | 2018-04-30 15:49:27 +0530 | [diff] [blame] | 379 | case PM_SECURE_RSA_AES: |
| 380 | ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2], |
| 381 | pm_arg[3]); |
| 382 | SMC_RET1(handle, (uint64_t)ret); |
| 383 | |
Rajan Vaja | 02d1842 | 2019-03-04 11:09:39 +0530 | [diff] [blame] | 384 | case PM_GET_CALLBACK_DATA: |
Naman Trivedi Manojbhai | beec83f | 2023-03-07 12:41:12 +0530 | [diff] [blame] | 385 | ret = pm_get_callbackdata(result, ARRAY_SIZE(result)); |
| 386 | if (ret != PM_RET_SUCCESS) { |
| 387 | result[0] = ret; |
| 388 | } |
| 389 | |
Rajan Vaja | 02d1842 | 2019-03-04 11:09:39 +0530 | [diff] [blame] | 390 | SMC_RET2(handle, |
| 391 | (uint64_t)result[0] | ((uint64_t)result[1] << 32), |
| 392 | (uint64_t)result[2] | ((uint64_t)result[3] << 32)); |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 393 | case PM_IOCTL: |
| 394 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 395 | uint32_t value = 0U; |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 396 | |
| 397 | ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], |
| 398 | pm_arg[3], &value); |
| 399 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); |
| 400 | } |
| 401 | |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 402 | case PM_QUERY_DATA: |
| 403 | { |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 404 | uint32_t data[4] = { 0 }; |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 405 | |
Rajan Vaja | cd82568 | 2020-11-23 21:33:39 -0800 | [diff] [blame] | 406 | pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], |
| 407 | pm_arg[3], data); |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 408 | SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32), |
| 409 | (uint64_t)data[2] | ((uint64_t)data[3] << 32)); |
| 410 | } |
| 411 | |
| 412 | case PM_CLOCK_ENABLE: |
| 413 | ret = pm_clock_enable(pm_arg[0]); |
| 414 | SMC_RET1(handle, (uint64_t)ret); |
| 415 | |
| 416 | case PM_CLOCK_DISABLE: |
| 417 | ret = pm_clock_disable(pm_arg[0]); |
| 418 | SMC_RET1(handle, (uint64_t)ret); |
| 419 | |
| 420 | case PM_CLOCK_GETSTATE: |
| 421 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 422 | uint32_t value = 0U; |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 423 | |
| 424 | ret = pm_clock_getstate(pm_arg[0], &value); |
| 425 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); |
| 426 | } |
| 427 | |
| 428 | case PM_CLOCK_SETDIVIDER: |
| 429 | ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]); |
| 430 | SMC_RET1(handle, (uint64_t)ret); |
| 431 | |
| 432 | case PM_CLOCK_GETDIVIDER: |
| 433 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 434 | uint32_t value = 0U; |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 435 | |
| 436 | ret = pm_clock_getdivider(pm_arg[0], &value); |
| 437 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); |
| 438 | } |
| 439 | |
| 440 | case PM_CLOCK_SETRATE: |
| 441 | ret = pm_clock_setrate(pm_arg[0], |
| 442 | ((uint64_t)pm_arg[2]) << 32 | pm_arg[1]); |
| 443 | |
| 444 | SMC_RET1(handle, (uint64_t)ret); |
| 445 | |
| 446 | case PM_CLOCK_GETRATE: |
| 447 | { |
Ronak Jain | f841467 | 2022-05-11 02:48:52 -0700 | [diff] [blame] | 448 | uint64_t value = 0; |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 449 | |
| 450 | ret = pm_clock_getrate(pm_arg[0], &value); |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 451 | SMC_RET2(handle, (uint64_t)ret | |
| 452 | (((uint64_t)value & 0xFFFFFFFFU) << 32U), |
| 453 | (value >> 32U) & 0xFFFFFFFFU); |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 454 | |
| 455 | } |
| 456 | |
| 457 | case PM_CLOCK_SETPARENT: |
| 458 | ret = pm_clock_setparent(pm_arg[0], pm_arg[1]); |
| 459 | SMC_RET1(handle, (uint64_t)ret); |
| 460 | |
| 461 | case PM_CLOCK_GETPARENT: |
| 462 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 463 | uint32_t value = 0U; |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 464 | |
| 465 | ret = pm_clock_getparent(pm_arg[0], &value); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 466 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 467 | } |
| 468 | |
Rajan Vaja | c7ee23d | 2018-02-14 23:10:54 -0800 | [diff] [blame] | 469 | case PM_GET_TRUSTZONE_VERSION: |
| 470 | SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 471 | ((uint64_t)ZYNQMP_TZ_VERSION << 32U)); |
Rajan Vaja | c7ee23d | 2018-02-14 23:10:54 -0800 | [diff] [blame] | 472 | |
Siva Durga Prasad Paladugu | 43b23a3 | 2018-04-27 16:26:47 +0530 | [diff] [blame] | 473 | case PM_SET_SUSPEND_MODE: |
| 474 | ret = pm_set_suspend_mode(pm_arg[0]); |
| 475 | SMC_RET1(handle, (uint64_t)ret); |
| 476 | |
Siva Durga Prasad Paladugu | f3994cc | 2018-05-01 11:12:55 +0530 | [diff] [blame] | 477 | case PM_SECURE_SHA: |
| 478 | ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2], |
| 479 | pm_arg[3]); |
| 480 | SMC_RET1(handle, (uint64_t)ret); |
| 481 | |
| 482 | case PM_SECURE_RSA: |
| 483 | ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2], |
| 484 | pm_arg[3]); |
| 485 | SMC_RET1(handle, (uint64_t)ret); |
| 486 | |
Siva Durga Prasad Paladugu | a4ed4b2 | 2018-04-30 20:06:58 +0530 | [diff] [blame] | 487 | case PM_SECURE_IMAGE: |
| 488 | { |
Siva Durga Prasad Paladugu | a4ed4b2 | 2018-04-30 20:06:58 +0530 | [diff] [blame] | 489 | ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2], |
| 490 | pm_arg[3], &result[0]); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 491 | SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), |
Siva Durga Prasad Paladugu | a4ed4b2 | 2018-04-30 20:06:58 +0530 | [diff] [blame] | 492 | result[1]); |
| 493 | } |
| 494 | |
Siva Durga Prasad Paladugu | 7c6516a | 2018-09-04 17:41:34 +0530 | [diff] [blame] | 495 | case PM_FPGA_READ: |
| 496 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 497 | uint32_t value = 0U; |
Siva Durga Prasad Paladugu | 7c6516a | 2018-09-04 17:41:34 +0530 | [diff] [blame] | 498 | |
| 499 | ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], |
| 500 | &value); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 501 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); |
Siva Durga Prasad Paladugu | 7c6516a | 2018-09-04 17:41:34 +0530 | [diff] [blame] | 502 | } |
| 503 | |
Siva Durga Prasad Paladugu | 8bd905b | 2018-09-04 18:05:50 +0530 | [diff] [blame] | 504 | case PM_SECURE_AES: |
| 505 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 506 | uint32_t value = 0U; |
Siva Durga Prasad Paladugu | 8bd905b | 2018-09-04 18:05:50 +0530 | [diff] [blame] | 507 | |
| 508 | ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 509 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); |
Siva Durga Prasad Paladugu | 8bd905b | 2018-09-04 18:05:50 +0530 | [diff] [blame] | 510 | } |
| 511 | |
Jolly Shah | a7cc5ee | 2019-01-02 12:27:00 -0800 | [diff] [blame] | 512 | case PM_PLL_SET_PARAMETER: |
| 513 | ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]); |
| 514 | SMC_RET1(handle, (uint64_t)ret); |
| 515 | |
Jolly Shah | cb2f45d | 2019-01-04 11:28:38 -0800 | [diff] [blame] | 516 | case PM_PLL_GET_PARAMETER: |
| 517 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 518 | uint32_t value = 0U; |
Jolly Shah | cb2f45d | 2019-01-04 11:28:38 -0800 | [diff] [blame] | 519 | |
| 520 | ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 521 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U)); |
Jolly Shah | cb2f45d | 2019-01-04 11:28:38 -0800 | [diff] [blame] | 522 | } |
| 523 | |
Jolly Shah | 1f0d585 | 2019-01-04 11:32:31 -0800 | [diff] [blame] | 524 | case PM_PLL_SET_MODE: |
| 525 | ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]); |
| 526 | SMC_RET1(handle, (uint64_t)ret); |
| 527 | |
Jolly Shah | 141421e | 2019-01-04 11:35:48 -0800 | [diff] [blame] | 528 | case PM_PLL_GET_MODE: |
| 529 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 530 | uint32_t mode = 0U; |
Jolly Shah | 141421e | 2019-01-04 11:35:48 -0800 | [diff] [blame] | 531 | |
| 532 | ret = pm_pll_get_mode(pm_arg[0], &mode); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 533 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U)); |
Jolly Shah | 141421e | 2019-01-04 11:35:48 -0800 | [diff] [blame] | 534 | } |
| 535 | |
Kalyani Akula | 6ebe483 | 2020-11-22 22:42:10 -0800 | [diff] [blame] | 536 | case PM_REGISTER_ACCESS: |
| 537 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 538 | uint32_t value = 0U; |
Kalyani Akula | 6ebe483 | 2020-11-22 22:42:10 -0800 | [diff] [blame] | 539 | |
| 540 | ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2], |
| 541 | pm_arg[3], &value); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 542 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); |
Kalyani Akula | 6ebe483 | 2020-11-22 22:42:10 -0800 | [diff] [blame] | 543 | } |
| 544 | |
VNSL Durga | deb1a36 | 2020-11-23 04:46:04 -0800 | [diff] [blame] | 545 | case PM_EFUSE_ACCESS: |
| 546 | { |
Naman Patel | 6c48034 | 2022-12-01 02:58:46 -0800 | [diff] [blame] | 547 | uint32_t value = 0U; |
VNSL Durga | deb1a36 | 2020-11-23 04:46:04 -0800 | [diff] [blame] | 548 | |
Vesa Jääskeläinen | 28f9ce5 | 2022-04-29 08:47:24 +0300 | [diff] [blame] | 549 | #if defined(ZYNQMP_SECURE_EFUSES) |
| 550 | if (is_caller_non_secure(flags)) { |
| 551 | SMC_RET1(handle, |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 552 | (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) | |
Vesa Jääskeläinen | 28f9ce5 | 2022-04-29 08:47:24 +0300 | [diff] [blame] | 553 | (uint64_t)PM_RET_ERROR_ACCESS); |
| 554 | } |
| 555 | #endif |
VNSL Durga | deb1a36 | 2020-11-23 04:46:04 -0800 | [diff] [blame] | 556 | ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 557 | SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); |
VNSL Durga | deb1a36 | 2020-11-23 04:46:04 -0800 | [diff] [blame] | 558 | } |
| 559 | |
Nava kishore Manne | 2af6d53 | 2022-01-13 13:29:36 +0530 | [diff] [blame] | 560 | case PM_FPGA_GET_VERSION: |
| 561 | case PM_FPGA_GET_FEATURE_LIST: |
| 562 | { |
Nava kishore Manne | 2af6d53 | 2022-01-13 13:29:36 +0530 | [diff] [blame] | 563 | uint32_t ret_payload[PAYLOAD_ARG_CNT]; |
| 564 | |
| 565 | PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK, |
| 566 | pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); |
| 567 | ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 568 | SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U, |
| 569 | (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U); |
Nava kishore Manne | 2af6d53 | 2022-01-13 13:29:36 +0530 | [diff] [blame] | 570 | } |
| 571 | |
Ronak Jain | 325bad1 | 2021-12-21 01:39:59 -0800 | [diff] [blame] | 572 | case PM_FEATURE_CHECK: |
| 573 | { |
Ronak Jain | f841467 | 2022-05-11 02:48:52 -0700 | [diff] [blame] | 574 | uint32_t version = 0; |
Ronak Jain | 325bad1 | 2021-12-21 01:39:59 -0800 | [diff] [blame] | 575 | uint32_t bit_mask[2] = {0}; |
| 576 | |
| 577 | ret = pm_feature_check(pm_arg[0], &version, bit_mask, |
| 578 | ARRAY_SIZE(bit_mask)); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 579 | SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U), |
| 580 | (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)); |
Ronak Jain | 325bad1 | 2021-12-21 01:39:59 -0800 | [diff] [blame] | 581 | } |
| 582 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 583 | default: |
Ronak Jain | 52de594 | 2022-01-20 23:11:18 -0800 | [diff] [blame] | 584 | /* Send request to the PMU */ |
| 585 | PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1], |
| 586 | pm_arg[2], pm_arg[3], pm_arg[4]); |
| 587 | ret = pm_ipi_send_sync(primary_proc, payload, result, |
| 588 | PAYLOAD_ARG_CNT); |
HariBabu Gattem | b0c70f5 | 2022-09-29 23:59:11 -0700 | [diff] [blame] | 589 | SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), |
| 590 | (uint64_t)result[1] | ((uint64_t)result[2] << 32U)); |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 591 | } |
| 592 | } |