| commit | 50702bab694368a97ef28df632f6e893970017a9 | [log] [tgz] |
|---|---|---|
| author | Tanmay Shah <tanmay.shah@amd.com> | Tue Sep 13 11:10:08 2022 -0700 |
| committer | Tanmay Shah <tanmay.shah@amd.com> | Tue Sep 13 11:19:01 2022 -0700 |
| tree | 9d27bc7c674ed4453541136c30168a6131f526f2 | |
| parent | 927ddb062a98248504d69df9a253992f76051f3f [diff] [blame] |
fix(zynqmp): ensure memory write finish with dsb() GICD reg write must complete before core goes to idle mode. Achieve this with dsb() barrier instruction in IPI ISR Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c index f24387a..82da57c 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c +++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -151,6 +151,8 @@ 0xffffffff); } + dsb(); + spin_unlock(&inc_lock); if (active_cores == 0) {