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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033#include <bl_common.h>
Vikram Kanigiri3ff77de2014-03-25 17:35:26 +000034#include <console.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010036#include <platform_def.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010037#include <string.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include "fvp_def.h"
39#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * Declarations of linker defined symbols which will help us find the layout
43 * of trusted SRAM
44 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045extern unsigned long __RO_START__;
46extern unsigned long __RO_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048extern unsigned long __COHERENT_RAM_START__;
49extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010050
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000051/*
52 * The next 2 constants identify the extents of the code & RO data region.
53 * These addresses are used by the MMU setup code and therefore they must be
54 * page-aligned. It is the responsibility of the linker script to ensure that
55 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
56 */
57#define BL2_RO_BASE (unsigned long)(&__RO_START__)
58#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
59
60/*
61 * The next 2 constants identify the extents of the coherent memory region.
62 * These addresses are used by the MMU setup code and therefore they must be
63 * page-aligned. It is the responsibility of the linker script to ensure that
64 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
65 * page-aligned addresses.
66 */
67#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
68#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010069
Achin Gupta4f6ad662013-10-25 09:08:21 +010070/* Data structure which holds the extents of the trusted SRAM for BL2 */
Dan Handleye2712bc2014-04-10 15:37:22 +010071static meminfo_t bl2_tzram_layout
Achin Gupta4f6ad662013-10-25 09:08:21 +010072__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
Sandrine Bailleux204aa032013-10-28 15:14:00 +000073 section("tzfw_coherent_mem")));
Achin Guptae4d084e2014-02-19 17:18:23 +000074
Juan Castillo48e84b32014-08-12 13:51:51 +010075/* Assert that BL3-1 parameters fit in shared memory */
76CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
Juan Castillo42a617d2014-09-24 10:00:06 +010077 (FVP_SHARED_MEM_BASE + FVP_SHARED_MEM_SIZE),
Juan Castillo48e84b32014-08-12 13:51:51 +010078 assert_bl31_params_do_not_fit_in_shared_memory);
79
Achin Guptae4d084e2014-02-19 17:18:23 +000080/*******************************************************************************
Vikram Kanigirida567432014-04-15 18:08:08 +010081 * Reference to structures which holds the arguments which need to be passed
Achin Guptae4d084e2014-02-19 17:18:23 +000082 * to BL31
83 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +010084static bl31_params_t *bl2_to_bl31_params;
Vikram Kanigirida567432014-04-15 18:08:08 +010085static entry_point_info_t *bl31_ep_info;
Achin Gupta4f6ad662013-10-25 09:08:21 +010086
Dan Handleye2712bc2014-04-10 15:37:22 +010087meminfo_t *bl2_plat_sec_mem_layout(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010088{
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000089 return &bl2_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010090}
91
Achin Guptae4d084e2014-02-19 17:18:23 +000092/*******************************************************************************
Vikram Kanigirida567432014-04-15 18:08:08 +010093 * This function assigns a pointer to the memory that the platform has kept
94 * aside to pass platform specific and trusted firmware related information
95 * to BL31. This memory is allocated by allocating memory to
96 * bl2_to_bl31_params_mem_t structure which is a superset of all the
97 * structure whose information is passed to BL31
98 * NOTE: This function should be called only once and should be done
99 * before generating params to BL31
100 ******************************************************************************/
101bl31_params_t *bl2_plat_get_bl31_params(void)
102{
103 bl2_to_bl31_params_mem_t *bl31_params_mem;
104
Vikram Kanigirida567432014-04-15 18:08:08 +0100105 /*
106 * Allocate the memory for all the arguments that needs to
107 * be passed to BL31
108 */
109 bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
110 memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t));
111
112 /* Assign memory for TF related information */
113 bl2_to_bl31_params = &bl31_params_mem->bl31_params;
114 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
115
Vikram Kanigirida567432014-04-15 18:08:08 +0100116 /* Fill BL31 related information */
117 bl31_ep_info = &bl31_params_mem->bl31_ep_info;
118 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
119 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
120 VERSION_1, 0);
121
122 /* Fill BL32 related information if it exists */
123 if (BL32_BASE) {
124 bl2_to_bl31_params->bl32_ep_info =
125 &bl31_params_mem->bl32_ep_info;
126 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info,
127 PARAM_EP, VERSION_1, 0);
128 bl2_to_bl31_params->bl32_image_info =
129 &bl31_params_mem->bl32_image_info;
130 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
131 PARAM_IMAGE_BINARY,
132 VERSION_1, 0);
Vikram Kanigirida567432014-04-15 18:08:08 +0100133 }
134
135 /* Fill BL33 related information */
136 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info;
137 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
138 PARAM_EP, VERSION_1, 0);
139 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
140 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
141 VERSION_1, 0);
Vikram Kanigirida567432014-04-15 18:08:08 +0100142
143 return bl2_to_bl31_params;
144}
145
Vikram Kanigirida567432014-04-15 18:08:08 +0100146
147/*******************************************************************************
148 * This function returns a pointer to the shared memory that the platform
149 * has kept to point to entry point information of BL31 to BL2
Achin Guptae4d084e2014-02-19 17:18:23 +0000150 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100151struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
Harry Liebel561cd332014-02-14 14:42:48 +0000152{
Andrew Thoelkea55566d2014-05-28 22:22:55 +0100153#if DEBUG
154 bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL;
155#endif
Vikram Kanigirida567432014-04-15 18:08:08 +0100156 return bl31_ep_info;
Harry Liebel561cd332014-02-14 14:42:48 +0000157}
158
Vikram Kanigirida567432014-04-15 18:08:08 +0100159
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160/*******************************************************************************
161 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
162 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
163 * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
164 ******************************************************************************/
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +0100165void bl2_early_platform_setup(meminfo_t *mem_layout)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166{
Vikram Kanigiri3684abf2014-03-27 14:33:15 +0000167 /* Initialize the console to provide early debug support */
Soby Mathew69817f72014-07-14 15:43:21 +0100168 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +0000169
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170 /* Setup the BL2 memory layout */
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100171 bl2_tzram_layout = *mem_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172
173 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +0100174 fvp_config_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175}
176
177/*******************************************************************************
Sandrine Bailleux942f4052013-11-19 17:14:22 +0000178 * Perform platform specific setup. For now just initialize the memory location
179 * to use for passing arguments to BL31.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100181void bl2_platform_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182{
Harry Liebelcef93392014-04-01 19:27:38 +0100183 /*
184 * Do initial security configuration to allow DRAM/device access. On
185 * Base FVP only DRAM security is programmable (via TrustZone), but
186 * other platforms might have more programmable security devices
187 * present.
188 */
Dan Handleyea451572014-05-15 14:53:30 +0100189 fvp_security_setup();
Harry Liebelcef93392014-04-01 19:27:38 +0100190
James Morrissey9d72b4e2014-02-10 17:04:32 +0000191 /* Initialise the IO layer and register platform IO devices */
Dan Handleyea451572014-05-15 14:53:30 +0100192 fvp_io_setup();
Vikram Kanigirida567432014-04-15 18:08:08 +0100193}
Achin Guptaa3050ed2014-02-19 17:52:35 +0000194
Vikram Kanigirida567432014-04-15 18:08:08 +0100195/* Flush the TF params and the TF plat params */
196void bl2_plat_flush_bl31_params(void)
197{
198 flush_dcache_range((unsigned long)PARAMS_BASE, \
199 sizeof(bl2_to_bl31_params_mem_t));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200}
201
Vikram Kanigirida567432014-04-15 18:08:08 +0100202
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203/*******************************************************************************
204 * Perform the very early platform specific architectural setup here. At the
205 * moment this is only intializes the mmu in a quick and dirty way.
206 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +0100207void bl2_plat_arch_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208{
Dan Handleyea451572014-05-15 14:53:30 +0100209 fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
210 bl2_tzram_layout.total_size,
211 BL2_RO_BASE,
212 BL2_RO_LIMIT,
213 BL2_COHERENT_RAM_BASE,
214 BL2_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215}
Vikram Kanigirida567432014-04-15 18:08:08 +0100216
217/*******************************************************************************
218 * Before calling this function BL31 is loaded in memory and its entrypoint
219 * is set by load_image. This is a placeholder for the platform to change
220 * the entrypoint of BL31 and set SPSR and security state.
221 * On FVP we are only setting the security state, entrypoint
222 ******************************************************************************/
223void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
224 entry_point_info_t *bl31_ep_info)
225{
226 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
227 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
228 DISABLE_ALL_EXCEPTIONS);
229}
230
231
232/*******************************************************************************
233 * Before calling this function BL32 is loaded in memory and its entrypoint
234 * is set by load_image. This is a placeholder for the platform to change
235 * the entrypoint of BL32 and set SPSR and security state.
236 * On FVP we are only setting the security state, entrypoint
237 ******************************************************************************/
238void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
239 entry_point_info_t *bl32_ep_info)
240{
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100241 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
242 bl32_ep_info->spsr = fvp_get_spsr_for_bl32_entry();
Vikram Kanigirida567432014-04-15 18:08:08 +0100243}
244
245/*******************************************************************************
246 * Before calling this function BL33 is loaded in memory and its entrypoint
247 * is set by load_image. This is a placeholder for the platform to change
248 * the entrypoint of BL33 and set SPSR and security state.
249 * On FVP we are only setting the security state, entrypoint
250 ******************************************************************************/
251void bl2_plat_set_bl33_ep_info(image_info_t *image,
252 entry_point_info_t *bl33_ep_info)
253{
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100254 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
255 bl33_ep_info->spsr = fvp_get_spsr_for_bl33_entry();
Vikram Kanigirida567432014-04-15 18:08:08 +0100256}
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100257
258
259/*******************************************************************************
260 * Populate the extents of memory available for loading BL32
261 ******************************************************************************/
262void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
263{
264 /*
265 * Populate the extents of memory available for loading BL32.
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100266 */
267 bl32_meminfo->total_base = BL32_BASE;
268 bl32_meminfo->free_base = BL32_BASE;
269 bl32_meminfo->total_size =
Sandrine Bailleux5ac3cc92014-05-20 17:22:24 +0100270 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100271 bl32_meminfo->free_size =
Sandrine Bailleux5ac3cc92014-05-20 17:22:24 +0100272 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100273}
274
275
276/*******************************************************************************
277 * Populate the extents of memory available for loading BL33
278 ******************************************************************************/
279void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
280{
281 bl33_meminfo->total_base = DRAM_BASE;
Juan Castillo7055ca42014-05-16 15:33:15 +0100282 bl33_meminfo->total_size = DRAM_SIZE - DRAM1_SEC_SIZE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100283 bl33_meminfo->free_base = DRAM_BASE;
Juan Castillo7055ca42014-05-16 15:33:15 +0100284 bl33_meminfo->free_size = DRAM_SIZE - DRAM1_SEC_SIZE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100285}