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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <string.h>
32#include <assert.h>
33#include <arch_helpers.h>
34#include <platform.h>
35#include <bl2.h>
36#include <bl_common.h>
37
38/*******************************************************************************
39 * Declarations of linker defined symbols which will help us find the layout
40 * of trusted SRAM
41 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000042extern unsigned long __RO_START__;
43extern unsigned long __RO_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045extern unsigned long __COHERENT_RAM_START__;
46extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048/*
49 * The next 2 constants identify the extents of the code & RO data region.
50 * These addresses are used by the MMU setup code and therefore they must be
51 * page-aligned. It is the responsibility of the linker script to ensure that
52 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
53 */
54#define BL2_RO_BASE (unsigned long)(&__RO_START__)
55#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
56
57/*
58 * The next 2 constants identify the extents of the coherent memory region.
59 * These addresses are used by the MMU setup code and therefore they must be
60 * page-aligned. It is the responsibility of the linker script to ensure that
61 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
62 * page-aligned addresses.
63 */
64#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
65#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010066
67/* Pointer to memory visible to both BL2 and BL31 for passing data */
68extern unsigned char **bl2_el_change_mem_ptr;
69
70/* Data structure which holds the extents of the trusted SRAM for BL2 */
71static meminfo bl2_tzram_layout
72__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
Sandrine Bailleux204aa032013-10-28 15:14:00 +000073 section("tzfw_coherent_mem")));
Achin Gupta4f6ad662013-10-25 09:08:21 +010074
Achin Gupta4f6ad662013-10-25 09:08:21 +010075meminfo bl2_get_sec_mem_layout(void)
76{
77 return bl2_tzram_layout;
78}
79
Achin Gupta4f6ad662013-10-25 09:08:21 +010080/*******************************************************************************
81 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
82 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
83 * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
84 ******************************************************************************/
85void bl2_early_platform_setup(meminfo *mem_layout,
86 void *data)
87{
88 /* Setup the BL2 memory layout */
89 bl2_tzram_layout.total_base = mem_layout->total_base;
90 bl2_tzram_layout.total_size = mem_layout->total_size;
91 bl2_tzram_layout.free_base = mem_layout->free_base;
92 bl2_tzram_layout.free_size = mem_layout->free_size;
93 bl2_tzram_layout.attr = mem_layout->attr;
94 bl2_tzram_layout.next = 0;
95
96 /* Initialize the platform config for future decision making */
97 platform_config_setup();
98
99 return;
100}
101
102/*******************************************************************************
Sandrine Bailleux942f4052013-11-19 17:14:22 +0000103 * Perform platform specific setup. For now just initialize the memory location
104 * to use for passing arguments to BL31.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 ******************************************************************************/
106void bl2_platform_setup()
107{
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 /* Use the Trusted DRAM for passing args to BL31 */
109 bl2_el_change_mem_ptr = (unsigned char **) TZDRAM_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110}
111
112/*******************************************************************************
113 * Perform the very early platform specific architectural setup here. At the
114 * moment this is only intializes the mmu in a quick and dirty way.
115 ******************************************************************************/
116void bl2_plat_arch_setup()
117{
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118 configure_mmu(&bl2_tzram_layout,
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000119 BL2_RO_BASE,
120 BL2_RO_LIMIT,
121 BL2_COHERENT_RAM_BASE,
122 BL2_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123}