blob: 7a3add5f81d2f4dc9e7759140d94949909b5790e [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033#include <bl_common.h>
Vikram Kanigiri3ff77de2014-03-25 17:35:26 +000034#include <console.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010036#include <platform_def.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010037#include <string.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include "fvp_def.h"
39#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * Declarations of linker defined symbols which will help us find the layout
43 * of trusted SRAM
44 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045extern unsigned long __RO_START__;
46extern unsigned long __RO_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048extern unsigned long __COHERENT_RAM_START__;
49extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010050
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000051/*
52 * The next 2 constants identify the extents of the code & RO data region.
53 * These addresses are used by the MMU setup code and therefore they must be
54 * page-aligned. It is the responsibility of the linker script to ensure that
55 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
56 */
57#define BL2_RO_BASE (unsigned long)(&__RO_START__)
58#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
59
60/*
61 * The next 2 constants identify the extents of the coherent memory region.
62 * These addresses are used by the MMU setup code and therefore they must be
63 * page-aligned. It is the responsibility of the linker script to ensure that
64 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
65 * page-aligned addresses.
66 */
67#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
68#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010069
Achin Gupta4f6ad662013-10-25 09:08:21 +010070/* Data structure which holds the extents of the trusted SRAM for BL2 */
Dan Handleye2712bc2014-04-10 15:37:22 +010071static meminfo_t bl2_tzram_layout
Achin Gupta4f6ad662013-10-25 09:08:21 +010072__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
Sandrine Bailleux204aa032013-10-28 15:14:00 +000073 section("tzfw_coherent_mem")));
Achin Guptae4d084e2014-02-19 17:18:23 +000074
75/*******************************************************************************
Vikram Kanigirida567432014-04-15 18:08:08 +010076 * Reference to structures which holds the arguments which need to be passed
Achin Guptae4d084e2014-02-19 17:18:23 +000077 * to BL31
78 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +010079static bl31_params_t *bl2_to_bl31_params;
Vikram Kanigirida567432014-04-15 18:08:08 +010080static entry_point_info_t *bl31_ep_info;
Achin Gupta4f6ad662013-10-25 09:08:21 +010081
Dan Handleye2712bc2014-04-10 15:37:22 +010082meminfo_t *bl2_plat_sec_mem_layout(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010083{
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000084 return &bl2_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010085}
86
Achin Guptae4d084e2014-02-19 17:18:23 +000087/*******************************************************************************
Vikram Kanigirida567432014-04-15 18:08:08 +010088 * This function assigns a pointer to the memory that the platform has kept
89 * aside to pass platform specific and trusted firmware related information
90 * to BL31. This memory is allocated by allocating memory to
91 * bl2_to_bl31_params_mem_t structure which is a superset of all the
92 * structure whose information is passed to BL31
93 * NOTE: This function should be called only once and should be done
94 * before generating params to BL31
95 ******************************************************************************/
96bl31_params_t *bl2_plat_get_bl31_params(void)
97{
98 bl2_to_bl31_params_mem_t *bl31_params_mem;
99
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100100#if TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
Vikram Kanigirida567432014-04-15 18:08:08 +0100101 /*
102 * Ensure that the secure DRAM memory used for passing BL31 arguments
103 * does not overlap with the BL32_BASE.
104 */
105 assert(BL32_BASE > PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t));
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100106#endif
Vikram Kanigirida567432014-04-15 18:08:08 +0100107
108 /*
109 * Allocate the memory for all the arguments that needs to
110 * be passed to BL31
111 */
112 bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
113 memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t));
114
115 /* Assign memory for TF related information */
116 bl2_to_bl31_params = &bl31_params_mem->bl31_params;
117 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
118
Vikram Kanigirida567432014-04-15 18:08:08 +0100119 /* Fill BL31 related information */
120 bl31_ep_info = &bl31_params_mem->bl31_ep_info;
121 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
122 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
123 VERSION_1, 0);
124
125 /* Fill BL32 related information if it exists */
126 if (BL32_BASE) {
127 bl2_to_bl31_params->bl32_ep_info =
128 &bl31_params_mem->bl32_ep_info;
129 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info,
130 PARAM_EP, VERSION_1, 0);
131 bl2_to_bl31_params->bl32_image_info =
132 &bl31_params_mem->bl32_image_info;
133 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
134 PARAM_IMAGE_BINARY,
135 VERSION_1, 0);
Vikram Kanigirida567432014-04-15 18:08:08 +0100136 }
137
138 /* Fill BL33 related information */
139 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info;
140 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
141 PARAM_EP, VERSION_1, 0);
142 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
143 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
144 VERSION_1, 0);
Vikram Kanigirida567432014-04-15 18:08:08 +0100145
146 return bl2_to_bl31_params;
147}
148
Vikram Kanigirida567432014-04-15 18:08:08 +0100149
150/*******************************************************************************
151 * This function returns a pointer to the shared memory that the platform
152 * has kept to point to entry point information of BL31 to BL2
Achin Guptae4d084e2014-02-19 17:18:23 +0000153 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100154struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
Harry Liebel561cd332014-02-14 14:42:48 +0000155{
Andrew Thoelkea55566d2014-05-28 22:22:55 +0100156#if DEBUG
157 bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL;
158#endif
Vikram Kanigirida567432014-04-15 18:08:08 +0100159 return bl31_ep_info;
Harry Liebel561cd332014-02-14 14:42:48 +0000160}
161
Vikram Kanigirida567432014-04-15 18:08:08 +0100162
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163/*******************************************************************************
164 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
165 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
166 * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
167 ******************************************************************************/
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +0100168void bl2_early_platform_setup(meminfo_t *mem_layout)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169{
Vikram Kanigiri3684abf2014-03-27 14:33:15 +0000170 /* Initialize the console to provide early debug support */
171 console_init(PL011_UART0_BASE);
172
Achin Gupta4f6ad662013-10-25 09:08:21 +0100173 /* Setup the BL2 memory layout */
174 bl2_tzram_layout.total_base = mem_layout->total_base;
175 bl2_tzram_layout.total_size = mem_layout->total_size;
176 bl2_tzram_layout.free_base = mem_layout->free_base;
177 bl2_tzram_layout.free_size = mem_layout->free_size;
178 bl2_tzram_layout.attr = mem_layout->attr;
179 bl2_tzram_layout.next = 0;
180
181 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +0100182 fvp_config_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183}
184
185/*******************************************************************************
Sandrine Bailleux942f4052013-11-19 17:14:22 +0000186 * Perform platform specific setup. For now just initialize the memory location
187 * to use for passing arguments to BL31.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +0100189void bl2_platform_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190{
Harry Liebelcef93392014-04-01 19:27:38 +0100191 /*
192 * Do initial security configuration to allow DRAM/device access. On
193 * Base FVP only DRAM security is programmable (via TrustZone), but
194 * other platforms might have more programmable security devices
195 * present.
196 */
Dan Handleyea451572014-05-15 14:53:30 +0100197 fvp_security_setup();
Harry Liebelcef93392014-04-01 19:27:38 +0100198
James Morrissey9d72b4e2014-02-10 17:04:32 +0000199 /* Initialise the IO layer and register platform IO devices */
Dan Handleyea451572014-05-15 14:53:30 +0100200 fvp_io_setup();
Vikram Kanigirida567432014-04-15 18:08:08 +0100201}
Achin Guptaa3050ed2014-02-19 17:52:35 +0000202
Vikram Kanigirida567432014-04-15 18:08:08 +0100203/* Flush the TF params and the TF plat params */
204void bl2_plat_flush_bl31_params(void)
205{
206 flush_dcache_range((unsigned long)PARAMS_BASE, \
207 sizeof(bl2_to_bl31_params_mem_t));
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208}
209
Vikram Kanigirida567432014-04-15 18:08:08 +0100210
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211/*******************************************************************************
212 * Perform the very early platform specific architectural setup here. At the
213 * moment this is only intializes the mmu in a quick and dirty way.
214 ******************************************************************************/
215void bl2_plat_arch_setup()
216{
Dan Handleyea451572014-05-15 14:53:30 +0100217 fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
218 bl2_tzram_layout.total_size,
219 BL2_RO_BASE,
220 BL2_RO_LIMIT,
221 BL2_COHERENT_RAM_BASE,
222 BL2_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100223}
Vikram Kanigirida567432014-04-15 18:08:08 +0100224
225/*******************************************************************************
226 * Before calling this function BL31 is loaded in memory and its entrypoint
227 * is set by load_image. This is a placeholder for the platform to change
228 * the entrypoint of BL31 and set SPSR and security state.
229 * On FVP we are only setting the security state, entrypoint
230 ******************************************************************************/
231void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
232 entry_point_info_t *bl31_ep_info)
233{
234 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
235 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
236 DISABLE_ALL_EXCEPTIONS);
237}
238
239
240/*******************************************************************************
241 * Before calling this function BL32 is loaded in memory and its entrypoint
242 * is set by load_image. This is a placeholder for the platform to change
243 * the entrypoint of BL32 and set SPSR and security state.
244 * On FVP we are only setting the security state, entrypoint
245 ******************************************************************************/
246void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
247 entry_point_info_t *bl32_ep_info)
248{
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100249 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
250 bl32_ep_info->spsr = fvp_get_spsr_for_bl32_entry();
Vikram Kanigirida567432014-04-15 18:08:08 +0100251}
252
253/*******************************************************************************
254 * Before calling this function BL33 is loaded in memory and its entrypoint
255 * is set by load_image. This is a placeholder for the platform to change
256 * the entrypoint of BL33 and set SPSR and security state.
257 * On FVP we are only setting the security state, entrypoint
258 ******************************************************************************/
259void bl2_plat_set_bl33_ep_info(image_info_t *image,
260 entry_point_info_t *bl33_ep_info)
261{
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100262 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
263 bl33_ep_info->spsr = fvp_get_spsr_for_bl33_entry();
Vikram Kanigirida567432014-04-15 18:08:08 +0100264}
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100265
266
267/*******************************************************************************
268 * Populate the extents of memory available for loading BL32
269 ******************************************************************************/
270void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
271{
272 /*
273 * Populate the extents of memory available for loading BL32.
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100274 */
275 bl32_meminfo->total_base = BL32_BASE;
276 bl32_meminfo->free_base = BL32_BASE;
277 bl32_meminfo->total_size =
Sandrine Bailleux5ac3cc92014-05-20 17:22:24 +0100278 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100279 bl32_meminfo->free_size =
Sandrine Bailleux5ac3cc92014-05-20 17:22:24 +0100280 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100281 bl32_meminfo->attr = BOT_LOAD;
282 bl32_meminfo->next = 0;
283}
284
285
286/*******************************************************************************
287 * Populate the extents of memory available for loading BL33
288 ******************************************************************************/
289void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
290{
291 bl33_meminfo->total_base = DRAM_BASE;
Juan Castillo7055ca42014-05-16 15:33:15 +0100292 bl33_meminfo->total_size = DRAM_SIZE - DRAM1_SEC_SIZE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100293 bl33_meminfo->free_base = DRAM_BASE;
Juan Castillo7055ca42014-05-16 15:33:15 +0100294 bl33_meminfo->free_size = DRAM_SIZE - DRAM1_SEC_SIZE;
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100295 bl33_meminfo->attr = 0;
296 bl33_meminfo->attr = 0;
297}