Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
Anthony Steinhauser | 0f7e601 | 2020-01-07 15:44:06 -0800 | [diff] [blame] | 2 | * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 9 | #include <neoverse_n1.h> |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 10 | #include <cpuamu.h> |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 12 | #include <context.h> |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 13 | |
John Tsichritzis | fe6df39 | 2019-03-19 17:20:52 +0000 | [diff] [blame] | 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
John Tsichritzis | 7557c66 | 2019-06-03 13:54:30 +0100 | [diff] [blame] | 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 24 | .global neoverse_n1_errata_ic_trap_handler |
Pramod Kumar | f01ea60 | 2020-02-05 11:27:57 +0530 | [diff] [blame] | 25 | .global is_scu_present_in_dsu |
| 26 | |
| 27 | /* |
| 28 | * Check DSU is configured with SCU and L3 unit |
| 29 | * 1-> SCU present |
| 30 | * 0-> SCU not present |
| 31 | */ |
| 32 | func is_scu_present_in_dsu |
| 33 | mrs x0, CPUCFR_EL1 |
| 34 | ubfx x0, x0, #SCU_SHIFT, #1 |
| 35 | eor x0, x0, #1 |
| 36 | ret |
| 37 | endfunc is_scu_present_in_dsu |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 38 | |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 39 | /* -------------------------------------------------- |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 40 | * Errata Workaround for Neoverse N1 Erratum 1043202. |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 41 | * This applies to revision r0p0 and r1p0 of Neoverse N1. |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 42 | * Inputs: |
| 43 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 44 | * Shall clobber: x0-x17 |
| 45 | * -------------------------------------------------- |
| 46 | */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 47 | func errata_n1_1043202_wa |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 48 | /* Compare x0 against revision r1p0 */ |
| 49 | mov x17, x30 |
| 50 | bl check_errata_1043202 |
| 51 | cbz x0, 1f |
| 52 | |
| 53 | /* Apply instruction patching sequence */ |
| 54 | ldr x0, =0x0 |
| 55 | msr CPUPSELR_EL3, x0 |
| 56 | ldr x0, =0xF3BF8F2F |
| 57 | msr CPUPOR_EL3, x0 |
| 58 | ldr x0, =0xFFFFFFFF |
| 59 | msr CPUPMR_EL3, x0 |
| 60 | ldr x0, =0x800200071 |
| 61 | msr CPUPCR_EL3, x0 |
laurenw-arm | 33e58f3 | 2019-08-19 11:06:18 -0500 | [diff] [blame] | 62 | isb |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 63 | 1: |
| 64 | ret x17 |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 65 | endfunc errata_n1_1043202_wa |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 66 | |
| 67 | func check_errata_1043202 |
| 68 | /* Applies to r0p0 and r1p0 */ |
| 69 | mov x1, #0x10 |
| 70 | b cpu_rev_var_ls |
| 71 | endfunc check_errata_1043202 |
| 72 | |
Sami Mujawar | a8722e9 | 2019-05-10 14:28:37 +0100 | [diff] [blame] | 73 | /* -------------------------------------------------- |
| 74 | * Disable speculative loads if Neoverse N1 supports |
| 75 | * SSBS. |
| 76 | * |
| 77 | * Shall clobber: x0. |
| 78 | * -------------------------------------------------- |
| 79 | */ |
| 80 | func neoverse_n1_disable_speculative_loads |
| 81 | /* Check if the PE implements SSBS */ |
| 82 | mrs x0, id_aa64pfr1_el1 |
| 83 | tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) |
| 84 | b.eq 1f |
| 85 | |
| 86 | /* Disable speculative loads */ |
| 87 | msr SSBS, xzr |
Sami Mujawar | a8722e9 | 2019-05-10 14:28:37 +0100 | [diff] [blame] | 88 | |
| 89 | 1: |
| 90 | ret |
| 91 | endfunc neoverse_n1_disable_speculative_loads |
| 92 | |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 93 | /* -------------------------------------------------- |
lauwal01 | bd555f4 | 2019-06-24 11:23:50 -0500 | [diff] [blame] | 94 | * Errata Workaround for Neoverse N1 Errata #1073348 |
| 95 | * This applies to revision r0p0 and r1p0 of Neoverse N1. |
| 96 | * Inputs: |
| 97 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 98 | * Shall clobber: x0-x17 |
| 99 | * -------------------------------------------------- |
| 100 | */ |
| 101 | func errata_n1_1073348_wa |
| 102 | /* Compare x0 against revision r1p0 */ |
| 103 | mov x17, x30 |
| 104 | bl check_errata_1073348 |
| 105 | cbz x0, 1f |
| 106 | mrs x1, NEOVERSE_N1_CPUACTLR_EL1 |
| 107 | orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 |
| 108 | msr NEOVERSE_N1_CPUACTLR_EL1, x1 |
lauwal01 | bd555f4 | 2019-06-24 11:23:50 -0500 | [diff] [blame] | 109 | 1: |
| 110 | ret x17 |
| 111 | endfunc errata_n1_1073348_wa |
| 112 | |
| 113 | func check_errata_1073348 |
| 114 | /* Applies to r0p0 and r1p0 */ |
| 115 | mov x1, #0x10 |
| 116 | b cpu_rev_var_ls |
| 117 | endfunc check_errata_1073348 |
| 118 | |
| 119 | /* -------------------------------------------------- |
lauwal01 | 363ee3c | 2019-06-24 11:28:34 -0500 | [diff] [blame] | 120 | * Errata Workaround for Neoverse N1 Errata #1130799 |
| 121 | * This applies to revision <=r2p0 of Neoverse N1. |
| 122 | * Inputs: |
| 123 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 124 | * Shall clobber: x0-x17 |
| 125 | * -------------------------------------------------- |
| 126 | */ |
| 127 | func errata_n1_1130799_wa |
| 128 | /* Compare x0 against revision r2p0 */ |
| 129 | mov x17, x30 |
| 130 | bl check_errata_1130799 |
| 131 | cbz x0, 1f |
| 132 | mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 |
| 133 | orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 |
| 134 | msr NEOVERSE_N1_CPUACTLR2_EL1, x1 |
lauwal01 | 363ee3c | 2019-06-24 11:28:34 -0500 | [diff] [blame] | 135 | 1: |
| 136 | ret x17 |
| 137 | endfunc errata_n1_1130799_wa |
| 138 | |
| 139 | func check_errata_1130799 |
| 140 | /* Applies to <=r2p0 */ |
| 141 | mov x1, #0x20 |
| 142 | b cpu_rev_var_ls |
| 143 | endfunc check_errata_1130799 |
| 144 | |
| 145 | /* -------------------------------------------------- |
lauwal01 | f2adb13 | 2019-06-24 11:32:40 -0500 | [diff] [blame] | 146 | * Errata Workaround for Neoverse N1 Errata #1165347 |
| 147 | * This applies to revision <=r2p0 of Neoverse N1. |
| 148 | * Inputs: |
| 149 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 150 | * Shall clobber: x0-x17 |
| 151 | * -------------------------------------------------- |
| 152 | */ |
| 153 | func errata_n1_1165347_wa |
| 154 | /* Compare x0 against revision r2p0 */ |
| 155 | mov x17, x30 |
| 156 | bl check_errata_1165347 |
| 157 | cbz x0, 1f |
| 158 | mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 |
| 159 | orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 |
| 160 | orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 |
| 161 | msr NEOVERSE_N1_CPUACTLR2_EL1, x1 |
lauwal01 | f2adb13 | 2019-06-24 11:32:40 -0500 | [diff] [blame] | 162 | 1: |
| 163 | ret x17 |
| 164 | endfunc errata_n1_1165347_wa |
| 165 | |
| 166 | func check_errata_1165347 |
| 167 | /* Applies to <=r2p0 */ |
| 168 | mov x1, #0x20 |
| 169 | b cpu_rev_var_ls |
| 170 | endfunc check_errata_1165347 |
| 171 | |
| 172 | /* -------------------------------------------------- |
lauwal01 | e159044 | 2019-06-24 11:35:37 -0500 | [diff] [blame] | 173 | * Errata Workaround for Neoverse N1 Errata #1207823 |
| 174 | * This applies to revision <=r2p0 of Neoverse N1. |
| 175 | * Inputs: |
| 176 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 177 | * Shall clobber: x0-x17 |
| 178 | * -------------------------------------------------- |
| 179 | */ |
| 180 | func errata_n1_1207823_wa |
| 181 | /* Compare x0 against revision r2p0 */ |
| 182 | mov x17, x30 |
| 183 | bl check_errata_1207823 |
| 184 | cbz x0, 1f |
| 185 | mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 |
| 186 | orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 |
| 187 | msr NEOVERSE_N1_CPUACTLR2_EL1, x1 |
lauwal01 | e159044 | 2019-06-24 11:35:37 -0500 | [diff] [blame] | 188 | 1: |
| 189 | ret x17 |
| 190 | endfunc errata_n1_1207823_wa |
| 191 | |
| 192 | func check_errata_1207823 |
| 193 | /* Applies to <=r2p0 */ |
| 194 | mov x1, #0x20 |
| 195 | b cpu_rev_var_ls |
| 196 | endfunc check_errata_1207823 |
| 197 | |
| 198 | /* -------------------------------------------------- |
lauwal01 | 197f14c | 2019-06-24 11:38:53 -0500 | [diff] [blame] | 199 | * Errata Workaround for Neoverse N1 Errata #1220197 |
| 200 | * This applies to revision <=r2p0 of Neoverse N1. |
| 201 | * Inputs: |
| 202 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 203 | * Shall clobber: x0-x17 |
| 204 | * -------------------------------------------------- |
| 205 | */ |
| 206 | func errata_n1_1220197_wa |
| 207 | /* Compare x0 against revision r2p0 */ |
| 208 | mov x17, x30 |
| 209 | bl check_errata_1220197 |
| 210 | cbz x0, 1f |
| 211 | mrs x1, NEOVERSE_N1_CPUECTLR_EL1 |
| 212 | orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK |
| 213 | msr NEOVERSE_N1_CPUECTLR_EL1, x1 |
lauwal01 | 197f14c | 2019-06-24 11:38:53 -0500 | [diff] [blame] | 214 | 1: |
| 215 | ret x17 |
| 216 | endfunc errata_n1_1220197_wa |
| 217 | |
| 218 | func check_errata_1220197 |
| 219 | /* Applies to <=r2p0 */ |
| 220 | mov x1, #0x20 |
| 221 | b cpu_rev_var_ls |
| 222 | endfunc check_errata_1220197 |
| 223 | |
| 224 | /* -------------------------------------------------- |
lauwal01 | 07c2a23 | 2019-06-24 11:42:02 -0500 | [diff] [blame] | 225 | * Errata Workaround for Neoverse N1 Errata #1257314 |
| 226 | * This applies to revision <=r3p0 of Neoverse N1. |
| 227 | * Inputs: |
| 228 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 229 | * Shall clobber: x0-x17 |
| 230 | * -------------------------------------------------- |
| 231 | */ |
| 232 | func errata_n1_1257314_wa |
| 233 | /* Compare x0 against revision r3p0 */ |
| 234 | mov x17, x30 |
| 235 | bl check_errata_1257314 |
| 236 | cbz x0, 1f |
| 237 | mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 |
| 238 | orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 |
| 239 | msr NEOVERSE_N1_CPUACTLR3_EL1, x1 |
lauwal01 | 07c2a23 | 2019-06-24 11:42:02 -0500 | [diff] [blame] | 240 | 1: |
| 241 | ret x17 |
| 242 | endfunc errata_n1_1257314_wa |
| 243 | |
| 244 | func check_errata_1257314 |
| 245 | /* Applies to <=r3p0 */ |
| 246 | mov x1, #0x30 |
| 247 | b cpu_rev_var_ls |
| 248 | endfunc check_errata_1257314 |
| 249 | |
| 250 | /* -------------------------------------------------- |
lauwal01 | 42771af | 2019-06-24 11:44:58 -0500 | [diff] [blame] | 251 | * Errata Workaround for Neoverse N1 Errata #1262606 |
| 252 | * This applies to revision <=r3p0 of Neoverse N1. |
| 253 | * Inputs: |
| 254 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 255 | * Shall clobber: x0-x17 |
| 256 | * -------------------------------------------------- |
| 257 | */ |
| 258 | func errata_n1_1262606_wa |
| 259 | /* Compare x0 against revision r3p0 */ |
| 260 | mov x17, x30 |
| 261 | bl check_errata_1262606 |
| 262 | cbz x0, 1f |
| 263 | mrs x1, NEOVERSE_N1_CPUACTLR_EL1 |
| 264 | orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 |
| 265 | msr NEOVERSE_N1_CPUACTLR_EL1, x1 |
lauwal01 | 42771af | 2019-06-24 11:44:58 -0500 | [diff] [blame] | 266 | 1: |
| 267 | ret x17 |
| 268 | endfunc errata_n1_1262606_wa |
| 269 | |
| 270 | func check_errata_1262606 |
| 271 | /* Applies to <=r3p0 */ |
| 272 | mov x1, #0x30 |
| 273 | b cpu_rev_var_ls |
| 274 | endfunc check_errata_1262606 |
| 275 | |
| 276 | /* -------------------------------------------------- |
lauwal01 | 00396bf | 2019-06-24 11:47:30 -0500 | [diff] [blame] | 277 | * Errata Workaround for Neoverse N1 Errata #1262888 |
| 278 | * This applies to revision <=r3p0 of Neoverse N1. |
| 279 | * Inputs: |
| 280 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 281 | * Shall clobber: x0-x17 |
| 282 | * -------------------------------------------------- |
| 283 | */ |
| 284 | func errata_n1_1262888_wa |
| 285 | /* Compare x0 against revision r3p0 */ |
| 286 | mov x17, x30 |
| 287 | bl check_errata_1262888 |
| 288 | cbz x0, 1f |
| 289 | mrs x1, NEOVERSE_N1_CPUECTLR_EL1 |
| 290 | orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT |
| 291 | msr NEOVERSE_N1_CPUECTLR_EL1, x1 |
lauwal01 | 00396bf | 2019-06-24 11:47:30 -0500 | [diff] [blame] | 292 | 1: |
| 293 | ret x17 |
| 294 | endfunc errata_n1_1262888_wa |
| 295 | |
| 296 | func check_errata_1262888 |
| 297 | /* Applies to <=r3p0 */ |
| 298 | mov x1, #0x30 |
| 299 | b cpu_rev_var_ls |
| 300 | endfunc check_errata_1262888 |
| 301 | |
| 302 | /* -------------------------------------------------- |
lauwal01 | 644b6ed | 2019-06-24 11:49:01 -0500 | [diff] [blame] | 303 | * Errata Workaround for Neoverse N1 Errata #1275112 |
| 304 | * This applies to revision <=r3p0 of Neoverse N1. |
| 305 | * Inputs: |
| 306 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 307 | * Shall clobber: x0-x17 |
| 308 | * -------------------------------------------------- |
| 309 | */ |
| 310 | func errata_n1_1275112_wa |
| 311 | /* Compare x0 against revision r3p0 */ |
| 312 | mov x17, x30 |
| 313 | bl check_errata_1275112 |
| 314 | cbz x0, 1f |
| 315 | mrs x1, NEOVERSE_N1_CPUACTLR_EL1 |
| 316 | orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 |
| 317 | msr NEOVERSE_N1_CPUACTLR_EL1, x1 |
lauwal01 | 644b6ed | 2019-06-24 11:49:01 -0500 | [diff] [blame] | 318 | 1: |
| 319 | ret x17 |
| 320 | endfunc errata_n1_1275112_wa |
| 321 | |
| 322 | func check_errata_1275112 |
| 323 | /* Applies to <=r3p0 */ |
| 324 | mov x1, #0x30 |
| 325 | b cpu_rev_var_ls |
| 326 | endfunc check_errata_1275112 |
| 327 | |
| 328 | /* -------------------------------------------------- |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 329 | * Errata Workaround for Neoverse N1 Erratum 1315703. |
| 330 | * This applies to revision <= r3p0 of Neoverse N1. |
| 331 | * Inputs: |
| 332 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 333 | * Shall clobber: x0-x17 |
| 334 | * -------------------------------------------------- |
| 335 | */ |
| 336 | func errata_n1_1315703_wa |
| 337 | /* Compare x0 against revision r3p1 */ |
| 338 | mov x17, x30 |
| 339 | bl check_errata_1315703 |
| 340 | cbz x0, 1f |
| 341 | |
| 342 | mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 |
| 343 | orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 |
| 344 | msr NEOVERSE_N1_CPUACTLR2_EL1, x0 |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 345 | |
| 346 | 1: |
| 347 | ret x17 |
| 348 | endfunc errata_n1_1315703_wa |
| 349 | |
| 350 | func check_errata_1315703 |
| 351 | /* Applies to everything <= r3p0. */ |
| 352 | mov x1, #0x30 |
| 353 | b cpu_rev_var_ls |
| 354 | endfunc check_errata_1315703 |
| 355 | |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 356 | /* -------------------------------------------------- |
| 357 | * Errata Workaround for Neoverse N1 Erratum 1542419. |
| 358 | * This applies to revisions r3p0 - r4p0 of Neoverse N1 |
| 359 | * Inputs: |
| 360 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 361 | * Shall clobber: x0-x17 |
| 362 | * -------------------------------------------------- |
| 363 | */ |
| 364 | func errata_n1_1542419_wa |
| 365 | /* Compare x0 against revision r3p0 and r4p0 */ |
| 366 | mov x17, x30 |
| 367 | bl check_errata_1542419 |
| 368 | cbz x0, 1f |
| 369 | |
laurenw-arm | cd9a943 | 2019-10-11 15:45:24 -0500 | [diff] [blame] | 370 | /* Apply instruction patching sequence */ |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 371 | ldr x0, =0x0 |
| 372 | msr CPUPSELR_EL3, x0 |
| 373 | ldr x0, =0xEE670D35 |
| 374 | msr CPUPOR_EL3, x0 |
| 375 | ldr x0, =0xFFFF0FFF |
| 376 | msr CPUPMR_EL3, x0 |
| 377 | ldr x0, =0x08000020007D |
| 378 | msr CPUPCR_EL3, x0 |
| 379 | isb |
| 380 | 1: |
| 381 | ret x17 |
| 382 | endfunc errata_n1_1542419_wa |
| 383 | |
| 384 | func check_errata_1542419 |
| 385 | /* Applies to everything r3p0 - r4p0. */ |
| 386 | mov x1, #0x30 |
| 387 | mov x2, #0x40 |
| 388 | b cpu_rev_var_range |
| 389 | endfunc check_errata_1542419 |
| 390 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 391 | func neoverse_n1_reset_func |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 392 | mov x19, x30 |
John Tsichritzis | 1f9ff49 | 2019-03-04 16:41:26 +0000 | [diff] [blame] | 393 | |
Sami Mujawar | a8722e9 | 2019-05-10 14:28:37 +0100 | [diff] [blame] | 394 | bl neoverse_n1_disable_speculative_loads |
John Tsichritzis | 1f9ff49 | 2019-03-04 16:41:26 +0000 | [diff] [blame] | 395 | |
Louis Mayencourt | b58142b | 2019-04-18 14:34:11 +0100 | [diff] [blame] | 396 | /* Forces all cacheable atomic instructions to be near */ |
| 397 | mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 |
| 398 | orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 |
| 399 | msr NEOVERSE_N1_CPUACTLR2_EL1, x0 |
| 400 | isb |
| 401 | |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 402 | bl cpu_get_rev_var |
| 403 | mov x18, x0 |
| 404 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 405 | #if ERRATA_N1_1043202 |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 406 | mov x0, x18 |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 407 | bl errata_n1_1043202_wa |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 408 | #endif |
| 409 | |
lauwal01 | bd555f4 | 2019-06-24 11:23:50 -0500 | [diff] [blame] | 410 | #if ERRATA_N1_1073348 |
| 411 | mov x0, x18 |
| 412 | bl errata_n1_1073348_wa |
| 413 | #endif |
| 414 | |
lauwal01 | 363ee3c | 2019-06-24 11:28:34 -0500 | [diff] [blame] | 415 | #if ERRATA_N1_1130799 |
| 416 | mov x0, x18 |
| 417 | bl errata_n1_1130799_wa |
| 418 | #endif |
| 419 | |
lauwal01 | f2adb13 | 2019-06-24 11:32:40 -0500 | [diff] [blame] | 420 | #if ERRATA_N1_1165347 |
| 421 | mov x0, x18 |
| 422 | bl errata_n1_1165347_wa |
| 423 | #endif |
| 424 | |
lauwal01 | e159044 | 2019-06-24 11:35:37 -0500 | [diff] [blame] | 425 | #if ERRATA_N1_1207823 |
| 426 | mov x0, x18 |
| 427 | bl errata_n1_1207823_wa |
| 428 | #endif |
| 429 | |
lauwal01 | 197f14c | 2019-06-24 11:38:53 -0500 | [diff] [blame] | 430 | #if ERRATA_N1_1220197 |
| 431 | mov x0, x18 |
| 432 | bl errata_n1_1220197_wa |
| 433 | #endif |
| 434 | |
lauwal01 | 07c2a23 | 2019-06-24 11:42:02 -0500 | [diff] [blame] | 435 | #if ERRATA_N1_1257314 |
| 436 | mov x0, x18 |
| 437 | bl errata_n1_1257314_wa |
| 438 | #endif |
| 439 | |
lauwal01 | 42771af | 2019-06-24 11:44:58 -0500 | [diff] [blame] | 440 | #if ERRATA_N1_1262606 |
| 441 | mov x0, x18 |
| 442 | bl errata_n1_1262606_wa |
| 443 | #endif |
| 444 | |
lauwal01 | 00396bf | 2019-06-24 11:47:30 -0500 | [diff] [blame] | 445 | #if ERRATA_N1_1262888 |
| 446 | mov x0, x18 |
| 447 | bl errata_n1_1262888_wa |
| 448 | #endif |
| 449 | |
lauwal01 | 644b6ed | 2019-06-24 11:49:01 -0500 | [diff] [blame] | 450 | #if ERRATA_N1_1275112 |
| 451 | mov x0, x18 |
| 452 | bl errata_n1_1275112_wa |
| 453 | #endif |
| 454 | |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 455 | #if ERRATA_N1_1315703 |
| 456 | mov x0, x18 |
| 457 | bl errata_n1_1315703_wa |
| 458 | #endif |
| 459 | |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 460 | #if ERRATA_N1_1542419 |
| 461 | mov x0, x18 |
| 462 | bl errata_n1_1542419_wa |
| 463 | #endif |
| 464 | |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 465 | #if ENABLE_AMU |
| 466 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 467 | mrs x0, actlr_el3 |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 468 | orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 469 | msr actlr_el3, x0 |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 470 | |
| 471 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 472 | mrs x0, actlr_el2 |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 473 | orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 474 | msr actlr_el2, x0 |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 475 | |
| 476 | /* Enable group0 counters */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 477 | mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 478 | msr CPUAMCNTENSET_EL0, x0 |
Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 479 | #endif |
Louis Mayencourt | 8b8b13b | 2019-06-10 16:43:39 +0100 | [diff] [blame] | 480 | |
Manish Pandey | 3880a36 | 2020-01-24 11:54:44 +0000 | [diff] [blame] | 481 | #if NEOVERSE_N1_EXTERNAL_LLC |
| 482 | /* Some system may have External LLC, core needs to be made aware */ |
| 483 | mrs x0, NEOVERSE_N1_CPUECTLR_EL1 |
| 484 | orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT |
| 485 | msr NEOVERSE_N1_CPUECTLR_EL1, x0 |
| 486 | #endif |
| 487 | |
Louis Mayencourt | 8b8b13b | 2019-06-10 16:43:39 +0100 | [diff] [blame] | 488 | #if ERRATA_DSU_936184 |
| 489 | bl errata_dsu_936184_wa |
| 490 | #endif |
| 491 | |
lauwal01 | cf12f26 | 2019-06-27 11:03:25 -0500 | [diff] [blame] | 492 | isb |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 493 | ret x19 |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 494 | endfunc neoverse_n1_reset_func |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 495 | |
| 496 | /* --------------------------------------------- |
| 497 | * HW will do the cache maintenance while powering down |
| 498 | * --------------------------------------------- |
| 499 | */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 500 | func neoverse_n1_core_pwr_dwn |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 501 | /* --------------------------------------------- |
| 502 | * Enable CPU power down bit in power control register |
| 503 | * --------------------------------------------- |
| 504 | */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 505 | mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 |
| 506 | orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK |
| 507 | msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 508 | isb |
| 509 | ret |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 510 | endfunc neoverse_n1_core_pwr_dwn |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 511 | |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 512 | #if REPORT_ERRATA |
| 513 | /* |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 514 | * Errata printing function for Neoverse N1. Must follow AAPCS. |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 515 | */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 516 | func neoverse_n1_errata_report |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 517 | stp x8, x30, [sp, #-16]! |
| 518 | |
| 519 | bl cpu_get_rev_var |
| 520 | mov x8, x0 |
| 521 | |
| 522 | /* |
| 523 | * Report all errata. The revision-variant information is passed to |
| 524 | * checking functions of each errata. |
| 525 | */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 526 | report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 |
lauwal01 | bd555f4 | 2019-06-24 11:23:50 -0500 | [diff] [blame] | 527 | report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 |
lauwal01 | 363ee3c | 2019-06-24 11:28:34 -0500 | [diff] [blame] | 528 | report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 |
lauwal01 | f2adb13 | 2019-06-24 11:32:40 -0500 | [diff] [blame] | 529 | report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 |
lauwal01 | e159044 | 2019-06-24 11:35:37 -0500 | [diff] [blame] | 530 | report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 |
lauwal01 | 197f14c | 2019-06-24 11:38:53 -0500 | [diff] [blame] | 531 | report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 |
lauwal01 | 07c2a23 | 2019-06-24 11:42:02 -0500 | [diff] [blame] | 532 | report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 |
lauwal01 | 42771af | 2019-06-24 11:44:58 -0500 | [diff] [blame] | 533 | report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 |
lauwal01 | 00396bf | 2019-06-24 11:47:30 -0500 | [diff] [blame] | 534 | report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 |
lauwal01 | 644b6ed | 2019-06-24 11:49:01 -0500 | [diff] [blame] | 535 | report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 |
Andre Przywara | b934740 | 2019-05-20 14:57:06 +0100 | [diff] [blame] | 536 | report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 537 | report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 |
Louis Mayencourt | 8b8b13b | 2019-06-10 16:43:39 +0100 | [diff] [blame] | 538 | report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 539 | |
| 540 | ldp x8, x30, [sp], #16 |
| 541 | ret |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 542 | endfunc neoverse_n1_errata_report |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 543 | #endif |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 544 | |
| 545 | /* |
| 546 | * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB |
| 547 | * inner-shareable invalidation to an arbitrary address followed by a DSB. |
| 548 | * |
| 549 | * x1: Exception Syndrome |
| 550 | */ |
| 551 | func neoverse_n1_errata_ic_trap_handler |
| 552 | cmp x1, #NEOVERSE_N1_EC_IC_TRAP |
| 553 | b.ne 1f |
| 554 | tlbi vae3is, xzr |
| 555 | dsb sy |
| 556 | |
laurenw-arm | cd9a943 | 2019-10-11 15:45:24 -0500 | [diff] [blame] | 557 | # Skip the IC instruction itself |
| 558 | mrs x3, elr_el3 |
| 559 | add x3, x3, #4 |
| 560 | msr elr_el3, x3 |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 561 | |
| 562 | ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] |
| 563 | ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] |
| 564 | ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] |
| 565 | ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 566 | |
| 567 | #if IMAGE_BL31 && RAS_EXTENSION |
| 568 | /* |
| 569 | * Issue Error Synchronization Barrier to synchronize SErrors before |
| 570 | * exiting EL3. We're running with EAs unmasked, so any synchronized |
| 571 | * errors would be taken immediately; therefore no need to inspect |
| 572 | * DISR_EL1 register. |
| 573 | */ |
| 574 | esb |
| 575 | #endif |
Anthony Steinhauser | 0f7e601 | 2020-01-07 15:44:06 -0800 | [diff] [blame] | 576 | exception_return |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 577 | 1: |
| 578 | ret |
| 579 | endfunc neoverse_n1_errata_ic_trap_handler |
Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 580 | |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 581 | /* --------------------------------------------- |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 582 | * This function provides neoverse_n1 specific |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 583 | * register information for crash reporting. |
| 584 | * It needs to return with x6 pointing to |
| 585 | * a list of register names in ascii and |
| 586 | * x8 - x15 having values of registers to be |
| 587 | * reported. |
| 588 | * --------------------------------------------- |
| 589 | */ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 590 | .section .rodata.neoverse_n1_regs, "aS" |
| 591 | neoverse_n1_regs: /* The ascii list of register names to be reported */ |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 592 | .asciz "cpuectlr_el1", "" |
| 593 | |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 594 | func neoverse_n1_cpu_reg_dump |
| 595 | adr x6, neoverse_n1_regs |
| 596 | mrs x8, NEOVERSE_N1_CPUECTLR_EL1 |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 597 | ret |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 598 | endfunc neoverse_n1_cpu_reg_dump |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 599 | |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 600 | declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 601 | neoverse_n1_reset_func, \ |
laurenw-arm | 94accd3 | 2019-08-20 15:51:24 -0500 | [diff] [blame] | 602 | neoverse_n1_errata_ic_trap_handler, \ |
John Tsichritzis | 56369c1 | 2019-02-19 13:49:06 +0000 | [diff] [blame] | 603 | neoverse_n1_core_pwr_dwn |