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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Varun Wadekarb316e242015-05-19 16:48:04 +05307#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <platform_def.h>
10
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053014#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/console.h>
16#include <lib/el3_runtime/context_mgmt.h>
17#include <lib/mmio.h>
18#include <lib/psci/psci.h>
19#include <plat/common/platform.h>
20
Varun Wadekarb316e242015-05-19 16:48:04 +053021#include <memctrl.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053022#include <pmc.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053023#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080024#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053025#include <tegra_private.h>
26
27extern uint64_t tegra_bl31_phys_base;
Varun Wadekara78bb1b2015-08-07 10:03:00 +053028extern uint64_t tegra_sec_entry_point;
Varun Wadekarb316e242015-05-19 16:48:04 +053029
30/*
31 * The following platform setup functions are weakly defined. They
32 * provide typical implementations that will be overridden by a SoC.
33 */
Varun Wadekar99782e82017-07-05 17:44:12 -070034#pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early
Varun Wadekarb3421ce2017-12-27 18:10:12 -080035#pragma weak tegra_soc_cpu_standby
Varun Wadekara78bb1b2015-08-07 10:03:00 +053036#pragma weak tegra_soc_pwr_domain_suspend
37#pragma weak tegra_soc_pwr_domain_on
38#pragma weak tegra_soc_pwr_domain_off
39#pragma weak tegra_soc_pwr_domain_on_finish
Varun Wadekard22429d2016-03-18 14:35:28 -070040#pragma weak tegra_soc_pwr_domain_power_down_wfi
Varun Wadekar8b82fae2015-11-09 17:39:28 -080041#pragma weak tegra_soc_prepare_system_reset
Varun Wadekare5caeed2016-01-07 14:04:21 -080042#pragma weak tegra_soc_prepare_system_off
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070043#pragma weak tegra_soc_get_target_pwr_state
Varun Wadekarb316e242015-05-19 16:48:04 +053044
Anthony Zhou85a8fa02017-03-22 14:42:42 +080045int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
Varun Wadekar99782e82017-07-05 17:44:12 -070046{
47 return PSCI_E_NOT_SUPPORTED;
48}
49
Varun Wadekarb3421ce2017-12-27 18:10:12 -080050int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
51{
52 (void)cpu_state;
53 return PSCI_E_SUCCESS;
54}
55
Anthony Zhou85a8fa02017-03-22 14:42:42 +080056int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053057{
Anthony Zhou85a8fa02017-03-22 14:42:42 +080058 (void)target_state;
Varun Wadekarb316e242015-05-19 16:48:04 +053059 return PSCI_E_NOT_SUPPORTED;
60}
61
Anthony Zhou85a8fa02017-03-22 14:42:42 +080062int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +053063{
Anthony Zhou85a8fa02017-03-22 14:42:42 +080064 (void)mpidr;
Varun Wadekarb316e242015-05-19 16:48:04 +053065 return PSCI_E_SUCCESS;
66}
67
Anthony Zhou85a8fa02017-03-22 14:42:42 +080068int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053069{
Anthony Zhou85a8fa02017-03-22 14:42:42 +080070 (void)target_state;
Varun Wadekarb316e242015-05-19 16:48:04 +053071 return PSCI_E_SUCCESS;
72}
73
Anthony Zhou85a8fa02017-03-22 14:42:42 +080074int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +053075{
Anthony Zhou85a8fa02017-03-22 14:42:42 +080076 (void)target_state;
Varun Wadekarb316e242015-05-19 16:48:04 +053077 return PSCI_E_SUCCESS;
78}
79
Anthony Zhou85a8fa02017-03-22 14:42:42 +080080int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
Varun Wadekard22429d2016-03-18 14:35:28 -070081{
Anthony Zhou85a8fa02017-03-22 14:42:42 +080082 (void)target_state;
Varun Wadekard22429d2016-03-18 14:35:28 -070083 return PSCI_E_SUCCESS;
84}
85
Anthony Zhou85a8fa02017-03-22 14:42:42 +080086int32_t tegra_soc_prepare_system_reset(void)
Varun Wadekar8b82fae2015-11-09 17:39:28 -080087{
88 return PSCI_E_SUCCESS;
89}
90
Varun Wadekare5caeed2016-01-07 14:04:21 -080091__dead2 void tegra_soc_prepare_system_off(void)
92{
93 ERROR("Tegra System Off: operation not handled.\n");
94 panic();
95}
96
Anthony Zhou85a8fa02017-03-22 14:42:42 +080097plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
Varun Wadekarf2aa1be2016-06-07 12:00:06 -070098 const plat_local_state_t *states,
Anthony Zhou85a8fa02017-03-22 14:42:42 +080099 uint32_t ncpu)
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700100{
Varun Wadekar14eaede2016-09-01 14:51:59 -0700101 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800102 uint32_t num_cpu = ncpu;
103 const plat_local_state_t *local_state = states;
104
105 (void)lvl;
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700106
Anthony Zhou4408e882017-07-07 14:29:51 +0800107 assert(ncpu != 0U);
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700108
109 do {
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800110 temp = *local_state;
111 if ((temp < target)) {
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700112 target = temp;
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800113 }
114 --num_cpu;
115 local_state++;
116 } while (num_cpu != 0U);
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700117
118 return target;
119}
120
Varun Wadekarb316e242015-05-19 16:48:04 +0530121/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530122 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
123 * call to get the `power_state` parameter. This allows the platform to encode
124 * the appropriate State-ID field within the `power_state` parameter which can
125 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
126******************************************************************************/
127void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530128{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700129 /* all affinities use system suspend state id */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800130 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700131 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800132 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530133}
134
135/*******************************************************************************
136 * Handler called when an affinity instance is about to enter standby.
137 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530138void tegra_cpu_standby(plat_local_state_t cpu_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530139{
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -0700140 u_register_t saved_scr_el3;
141
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800142 (void)cpu_state;
143
Varun Wadekarb3421ce2017-12-27 18:10:12 -0800144 /* Tegra SoC specific handler */
145 if (tegra_soc_cpu_standby(cpu_state) != PSCI_E_SUCCESS)
146 ERROR("%s failed\n", __func__);
147
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -0700148 saved_scr_el3 = read_scr_el3();
149
150 /*
151 * As per ARM ARM D1.17.2, any physical IRQ interrupt received by the
152 * PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
153 * irrespective of the value of the PSTATE.I bit value.
154 */
155 write_scr_el3(saved_scr_el3 | SCR_IRQ_BIT);
156
Varun Wadekarb316e242015-05-19 16:48:04 +0530157 /*
158 * Enter standby state
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -0700159 *
160 * dsb & isb is good practice before using wfi to enter low power states
Varun Wadekarb316e242015-05-19 16:48:04 +0530161 */
162 dsb();
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -0700163 isb();
Varun Wadekarb316e242015-05-19 16:48:04 +0530164 wfi();
Vignesh Radhakrishnan16d82ae2018-04-20 14:31:41 -0700165
166 /*
167 * Restore saved scr_el3 that has IRQ bit cleared as we don't want EL3
168 * handling any further interrupts
169 */
170 write_scr_el3(saved_scr_el3);
Varun Wadekarb316e242015-05-19 16:48:04 +0530171}
172
173/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530174 * Handler called when an affinity instance is about to be turned on. The
175 * level and mpidr determine the affinity instance.
176 ******************************************************************************/
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800177int32_t tegra_pwr_domain_on(u_register_t mpidr)
Varun Wadekarb316e242015-05-19 16:48:04 +0530178{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530179 return tegra_soc_pwr_domain_on(mpidr);
Varun Wadekarb316e242015-05-19 16:48:04 +0530180}
181
182/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530183 * Handler called when a power domain is about to be turned off. The
184 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530185 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530186void tegra_pwr_domain_off(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530187{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800188 (void)tegra_soc_pwr_domain_off(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530189}
190
191/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700192 * Handler called when a power domain is about to be suspended. The
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530193 * target_state encodes the power state that each level should transition to.
Varun Wadekar99782e82017-07-05 17:44:12 -0700194 * This handler is called with SMP and data cache enabled, when
195 * HW_ASSISTED_COHERENCY = 0
196 ******************************************************************************/
197void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
198{
199 tegra_soc_pwr_domain_suspend_pwrdown_early(target_state);
200}
201
202/*******************************************************************************
203 * Handler called when a power domain is about to be suspended. The
204 * target_state encodes the power state that each level should transition to.
Varun Wadekarb316e242015-05-19 16:48:04 +0530205 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530206void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530207{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800208 (void)tegra_soc_pwr_domain_suspend(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530209
Varun Wadekara2c6be62016-08-01 22:16:21 -0700210 /* Disable console if we are entering deep sleep. */
211 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800212 PSTATE_ID_SOC_POWERDN) {
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100213 (void)console_flush();
214 console_switch_state(0);
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800215 }
Varun Wadekara2c6be62016-08-01 22:16:21 -0700216
Varun Wadekarb316e242015-05-19 16:48:04 +0530217 /* disable GICC */
218 tegra_gic_cpuif_deactivate();
219}
220
221/*******************************************************************************
Varun Wadekard22429d2016-03-18 14:35:28 -0700222 * Handler called at the end of the power domain suspend sequence. The
223 * target_state encodes the power state that each level should transition to.
224 ******************************************************************************/
225__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
226 *target_state)
227{
228 /* call the chip's power down handler */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800229 (void)tegra_soc_pwr_domain_power_down_wfi(target_state);
Varun Wadekard22429d2016-03-18 14:35:28 -0700230
Vignesh Radhakrishnan833d89c2017-05-25 10:31:42 -0700231 wfi();
Varun Wadekard22429d2016-03-18 14:35:28 -0700232 panic();
233}
234
235/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530236 * Handler called when a power domain has just been powered on after
237 * being turned off earlier. The target_state encodes the low power state that
238 * each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530239 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530240void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530241{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800242 const plat_params_from_bl2_t *plat_params;
Varun Wadekarb316e242015-05-19 16:48:04 +0530243
244 /*
Varun Wadekarb316e242015-05-19 16:48:04 +0530245 * Initialize the GIC cpu and distributor interfaces
246 */
Varun Wadekar77ef1ff2019-12-17 11:49:00 -0800247 tegra_gic_pcpu_init();
Varun Wadekarb316e242015-05-19 16:48:04 +0530248
249 /*
250 * Check if we are exiting from deep sleep.
251 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530252 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
253 PSTATE_ID_SOC_POWERDN) {
Varun Wadekarb316e242015-05-19 16:48:04 +0530254
Ambroise Vincent09a22e72019-05-29 14:04:16 +0100255 /* Restart console output. */
256 console_switch_state(CONSOLE_FLAG_RUNTIME);
Varun Wadekara2c6be62016-08-01 22:16:21 -0700257
Varun Wadekarb316e242015-05-19 16:48:04 +0530258 /*
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800259 * Restore Memory Controller settings as it loses state
260 * during system suspend.
Varun Wadekarb316e242015-05-19 16:48:04 +0530261 */
Varun Wadekar6eec6d62016-03-03 13:28:10 -0800262 tegra_memctrl_restore_settings();
Varun Wadekarb316e242015-05-19 16:48:04 +0530263
264 /*
265 * Security configuration to allow DRAM/device access.
266 */
267 plat_params = bl31_get_plat_params();
Varun Wadekar6bb62462015-10-06 12:49:31 +0530268 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800269 (uint32_t)plat_params->tzdram_size);
Varun Wadekard5f578a2016-06-01 19:34:37 -0700270
271 /*
272 * Set up the TZRAM memory aperture to allow only secure world
273 * access
274 */
275 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
Varun Wadekarb316e242015-05-19 16:48:04 +0530276 }
277
278 /*
279 * Reset hardware settings.
280 */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800281 (void)tegra_soc_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530282}
283
284/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530285 * Handler called when a power domain has just been powered on after
286 * having been suspended earlier. The target_state encodes the low power state
287 * that each level has woken up from.
Varun Wadekarb316e242015-05-19 16:48:04 +0530288 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530289void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Varun Wadekarb316e242015-05-19 16:48:04 +0530290{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530291 tegra_pwr_domain_on_finish(target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530292}
293
294/*******************************************************************************
295 * Handler called when the system wants to be powered off
296 ******************************************************************************/
297__dead2 void tegra_system_off(void)
298{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800299 INFO("Powering down system...\n");
300
301 tegra_soc_prepare_system_off();
Varun Wadekarb316e242015-05-19 16:48:04 +0530302}
303
304/*******************************************************************************
305 * Handler called when the system wants to be restarted.
306 ******************************************************************************/
307__dead2 void tegra_system_reset(void)
308{
Varun Wadekare5caeed2016-01-07 14:04:21 -0800309 INFO("Restarting system...\n");
310
Varun Wadekar8b82fae2015-11-09 17:39:28 -0800311 /* per-SoC system reset handler */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800312 (void)tegra_soc_prepare_system_reset();
Varun Wadekar8b82fae2015-11-09 17:39:28 -0800313
Varun Wadekarb316e242015-05-19 16:48:04 +0530314 /*
315 * Program the PMC in order to restart the system.
316 */
317 tegra_pmc_system_reset();
318}
319
320/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530321 * Handler called to check the validity of the power state parameter.
322 ******************************************************************************/
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800323int32_t tegra_validate_power_state(uint32_t power_state,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530324 psci_power_state_t *req_state)
325{
Anthony Zhou4408e882017-07-07 14:29:51 +0800326 assert(req_state != NULL);
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530327
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530328 return tegra_soc_validate_power_state(power_state, req_state);
329}
330
331/*******************************************************************************
332 * Platform handler called to check the validity of the non secure entrypoint.
333 ******************************************************************************/
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800334int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530335{
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800336 int32_t ret = PSCI_E_INVALID_ADDRESS;
337
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530338 /*
339 * Check if the non secure entrypoint lies within the non
340 * secure DRAM.
341 */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800342 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) {
343 ret = PSCI_E_SUCCESS;
344 }
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530345
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800346 return ret;
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530347}
348
349/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530350 * Export the platform handlers to enable psci to invoke them
351 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530352static const plat_psci_ops_t tegra_plat_psci_ops = {
353 .cpu_standby = tegra_cpu_standby,
354 .pwr_domain_on = tegra_pwr_domain_on,
355 .pwr_domain_off = tegra_pwr_domain_off,
Varun Wadekar99782e82017-07-05 17:44:12 -0700356 .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530357 .pwr_domain_suspend = tegra_pwr_domain_suspend,
358 .pwr_domain_on_finish = tegra_pwr_domain_on_finish,
359 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
Varun Wadekard22429d2016-03-18 14:35:28 -0700360 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi,
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530361 .system_off = tegra_system_off,
362 .system_reset = tegra_system_reset,
363 .validate_power_state = tegra_validate_power_state,
364 .validate_ns_entrypoint = tegra_validate_ns_entrypoint,
365 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state,
Varun Wadekarb316e242015-05-19 16:48:04 +0530366};
367
368/*******************************************************************************
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530369 * Export the platform specific power ops and initialize Power Controller
Varun Wadekarb316e242015-05-19 16:48:04 +0530370 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530371int plat_setup_psci_ops(uintptr_t sec_entrypoint,
372 const plat_psci_ops_t **psci_ops)
Varun Wadekarb316e242015-05-19 16:48:04 +0530373{
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530374 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } };
375
376 /*
377 * Flush entrypoint variable to PoC since it will be
378 * accessed after a reset with the caches turned off.
379 */
380 tegra_sec_entry_point = sec_entrypoint;
381 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t));
382
Varun Wadekarb316e242015-05-19 16:48:04 +0530383 /*
384 * Reset hardware settings.
385 */
Anthony Zhou85a8fa02017-03-22 14:42:42 +0800386 (void)tegra_soc_pwr_domain_on_finish(&target_state);
Varun Wadekarb316e242015-05-19 16:48:04 +0530387
388 /*
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530389 * Initialize PSCI ops struct
Varun Wadekarb316e242015-05-19 16:48:04 +0530390 */
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530391 *psci_ops = &tegra_plat_psci_ops;
Varun Wadekarb316e242015-05-19 16:48:04 +0530392
393 return 0;
394}
Varun Wadekar24975392016-05-05 14:13:30 -0700395
396/*******************************************************************************
397 * Platform handler to calculate the proper target power level at the
398 * specified affinity level
399 ******************************************************************************/
400plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
401 const plat_local_state_t *states,
402 unsigned int ncpu)
403{
Varun Wadekarf2aa1be2016-06-07 12:00:06 -0700404 return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
Varun Wadekar24975392016-05-05 14:13:30 -0700405}