Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A57_H |
| 8 | #define CORTEX_A57_H |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | |
| 10 | #include <lib/utils_def.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 11 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 12 | /* Cortex-A57 midr for revision 0 */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 13 | #define CORTEX_A57_MIDR U(0x410FD070) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 15 | /* Retention timer tick definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 16 | #define RETENTION_ENTRY_TICKS_2 U(0x1) |
| 17 | #define RETENTION_ENTRY_TICKS_8 U(0x2) |
| 18 | #define RETENTION_ENTRY_TICKS_32 U(0x3) |
| 19 | #define RETENTION_ENTRY_TICKS_64 U(0x4) |
| 20 | #define RETENTION_ENTRY_TICKS_128 U(0x5) |
| 21 | #define RETENTION_ENTRY_TICKS_256 U(0x6) |
| 22 | #define RETENTION_ENTRY_TICKS_512 U(0x7) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 23 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 24 | /******************************************************************************* |
| 25 | * CPU Extended Control register specific definitions. |
| 26 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 27 | #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 28 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 29 | #define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) |
| 30 | #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) |
| 31 | #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) |
| 32 | #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 33 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 34 | #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) |
| 35 | #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 36 | |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 37 | /******************************************************************************* |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 38 | * CPU Memory Error Syndrome register specific definitions. |
| 39 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 40 | #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 41 | |
| 42 | /******************************************************************************* |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 43 | * CPU Auxiliary Control register specific definitions. |
| 44 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 45 | #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 46 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 47 | #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 48 | #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 49 | #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) |
| 50 | #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) |
| 51 | #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) |
| 52 | #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) |
| 53 | #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 54 | #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 55 | #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) |
| 56 | #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) |
| 57 | #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 58 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 59 | /******************************************************************************* |
| 60 | * L2 Control register specific definitions. |
| 61 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 62 | #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 63 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 64 | #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 65 | #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 66 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 67 | #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) |
| 68 | #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 69 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 70 | #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) |
Varun Wadekar | 69ce101 | 2016-05-12 13:43:33 -0700 | [diff] [blame] | 71 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 72 | /******************************************************************************* |
| 73 | * L2 Extended Control register specific definitions. |
| 74 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 75 | #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 76 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 77 | #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) |
| 78 | #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 79 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 80 | /******************************************************************************* |
| 81 | * L2 Memory Error Syndrome register specific definitions. |
| 82 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 83 | #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 84 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 85 | #endif /* CORTEX_A57_H */ |