Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 7 | #ifndef __CORTEX_A57_H__ |
| 8 | #define __CORTEX_A57_H__ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | /* Cortex-A57 midr for revision 0 */ |
| 11 | #define CORTEX_A57_MIDR 0x410FD070 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 12 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 13 | /* Retention timer tick definitions */ |
| 14 | #define RETENTION_ENTRY_TICKS_2 0x1 |
| 15 | #define RETENTION_ENTRY_TICKS_8 0x2 |
| 16 | #define RETENTION_ENTRY_TICKS_32 0x3 |
| 17 | #define RETENTION_ENTRY_TICKS_64 0x4 |
| 18 | #define RETENTION_ENTRY_TICKS_128 0x5 |
| 19 | #define RETENTION_ENTRY_TICKS_256 0x6 |
| 20 | #define RETENTION_ENTRY_TICKS_512 0x7 |
| 21 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 22 | /******************************************************************************* |
| 23 | * CPU Extended Control register specific definitions. |
| 24 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 25 | #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 26 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 27 | #define CORTEX_A57_ECTLR_SMP_BIT (1 << 6) |
| 28 | #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) |
| 29 | #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) |
| 30 | #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 31 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 32 | #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 |
| 33 | #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 34 | |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 35 | /******************************************************************************* |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 36 | * CPU Memory Error Syndrome register specific definitions. |
| 37 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 38 | #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 41 | * CPU Auxiliary Control register specific definitions. |
| 42 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 43 | #define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 44 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 45 | #define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59) |
| 46 | #define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54) |
| 47 | #define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52) |
| 48 | #define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49) |
| 49 | #define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44) |
| 50 | #define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38) |
| 51 | #define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27) |
| 52 | #define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25) |
| 53 | #define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 54 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 55 | /******************************************************************************* |
| 56 | * L2 Control register specific definitions. |
| 57 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 58 | #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 59 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 60 | #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 |
| 61 | #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 62 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 63 | #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 |
| 64 | #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 65 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 66 | #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (1 << 21) |
Varun Wadekar | 69ce101 | 2016-05-12 13:43:33 -0700 | [diff] [blame] | 67 | |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 68 | /******************************************************************************* |
| 69 | * L2 Extended Control register specific definitions. |
| 70 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 71 | #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 72 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 73 | #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 |
| 74 | #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) |
Varun Wadekar | 3ce4e88 | 2015-08-21 15:52:51 +0530 | [diff] [blame] | 75 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 76 | /******************************************************************************* |
| 77 | * L2 Memory Error Syndrome register specific definitions. |
| 78 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame^] | 79 | #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 80 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 81 | #endif /* __CORTEX_A57_H__ */ |