Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 14 | #include <context.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <drivers/console.h> |
| 16 | #include <lib/el3_runtime/context_mgmt.h> |
| 17 | #include <lib/mmio.h> |
| 18 | #include <lib/psci/psci.h> |
| 19 | #include <plat/common/platform.h> |
| 20 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 21 | #include <memctrl.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 22 | #include <pmc.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 23 | #include <tegra_def.h> |
Harvey Hsieh | 9e083c7 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 24 | #include <tegra_platform.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 25 | #include <tegra_private.h> |
| 26 | |
| 27 | extern uint64_t tegra_bl31_phys_base; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 28 | extern uint64_t tegra_sec_entry_point; |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 29 | extern uint64_t tegra_console_base; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 30 | |
| 31 | /* |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 32 | * tegra_fake_system_suspend acts as a boolean var controlling whether |
| 33 | * we are going to take fake system suspend code or normal system suspend code |
| 34 | * path. This variable is set inside the sip call handlers,when the kernel |
| 35 | * requests a SIP call to set the suspend debug flags. |
| 36 | */ |
| 37 | uint8_t tegra_fake_system_suspend; |
| 38 | |
| 39 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 40 | * The following platform setup functions are weakly defined. They |
| 41 | * provide typical implementations that will be overridden by a SoC. |
| 42 | */ |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 43 | #pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early |
Varun Wadekar | b3421ce | 2017-12-27 18:10:12 -0800 | [diff] [blame] | 44 | #pragma weak tegra_soc_cpu_standby |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 45 | #pragma weak tegra_soc_pwr_domain_suspend |
| 46 | #pragma weak tegra_soc_pwr_domain_on |
| 47 | #pragma weak tegra_soc_pwr_domain_off |
| 48 | #pragma weak tegra_soc_pwr_domain_on_finish |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 49 | #pragma weak tegra_soc_pwr_domain_power_down_wfi |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 50 | #pragma weak tegra_soc_prepare_system_reset |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 51 | #pragma weak tegra_soc_prepare_system_off |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 52 | #pragma weak tegra_soc_get_target_pwr_state |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 53 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 54 | int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 55 | { |
| 56 | return PSCI_E_NOT_SUPPORTED; |
| 57 | } |
| 58 | |
Varun Wadekar | b3421ce | 2017-12-27 18:10:12 -0800 | [diff] [blame] | 59 | int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state) |
| 60 | { |
| 61 | (void)cpu_state; |
| 62 | return PSCI_E_SUCCESS; |
| 63 | } |
| 64 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 65 | int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 66 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 67 | (void)target_state; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 68 | return PSCI_E_NOT_SUPPORTED; |
| 69 | } |
| 70 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 71 | int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 72 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 73 | (void)mpidr; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 74 | return PSCI_E_SUCCESS; |
| 75 | } |
| 76 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 77 | int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 78 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 79 | (void)target_state; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 80 | return PSCI_E_SUCCESS; |
| 81 | } |
| 82 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 83 | int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 84 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 85 | (void)target_state; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 86 | return PSCI_E_SUCCESS; |
| 87 | } |
| 88 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 89 | int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 90 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 91 | (void)target_state; |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 92 | return PSCI_E_SUCCESS; |
| 93 | } |
| 94 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 95 | int32_t tegra_soc_prepare_system_reset(void) |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 96 | { |
| 97 | return PSCI_E_SUCCESS; |
| 98 | } |
| 99 | |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 100 | __dead2 void tegra_soc_prepare_system_off(void) |
| 101 | { |
| 102 | ERROR("Tegra System Off: operation not handled.\n"); |
| 103 | panic(); |
| 104 | } |
| 105 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 106 | plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 107 | const plat_local_state_t *states, |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 108 | uint32_t ncpu) |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 109 | { |
Varun Wadekar | 14eaede | 2016-09-01 14:51:59 -0700 | [diff] [blame] | 110 | plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 111 | uint32_t num_cpu = ncpu; |
| 112 | const plat_local_state_t *local_state = states; |
| 113 | |
| 114 | (void)lvl; |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 115 | |
Anthony Zhou | 4408e88 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 116 | assert(ncpu != 0U); |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 117 | |
| 118 | do { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 119 | temp = *local_state; |
| 120 | if ((temp < target)) { |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 121 | target = temp; |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 122 | } |
| 123 | --num_cpu; |
| 124 | local_state++; |
| 125 | } while (num_cpu != 0U); |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 126 | |
| 127 | return target; |
| 128 | } |
| 129 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 130 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 131 | * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` |
| 132 | * call to get the `power_state` parameter. This allows the platform to encode |
| 133 | * the appropriate State-ID field within the `power_state` parameter which can |
| 134 | * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. |
| 135 | ******************************************************************************/ |
| 136 | void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 137 | { |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 138 | /* all affinities use system suspend state id */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 139 | for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 140 | req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 141 | } |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | /******************************************************************************* |
| 145 | * Handler called when an affinity instance is about to enter standby. |
| 146 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 147 | void tegra_cpu_standby(plat_local_state_t cpu_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 148 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 149 | (void)cpu_state; |
| 150 | |
Varun Wadekar | b3421ce | 2017-12-27 18:10:12 -0800 | [diff] [blame] | 151 | /* Tegra SoC specific handler */ |
| 152 | if (tegra_soc_cpu_standby(cpu_state) != PSCI_E_SUCCESS) |
| 153 | ERROR("%s failed\n", __func__); |
| 154 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 155 | /* |
| 156 | * Enter standby state |
| 157 | * dsb is good practice before using wfi to enter low power states |
| 158 | */ |
| 159 | dsb(); |
| 160 | wfi(); |
| 161 | } |
| 162 | |
| 163 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 164 | * Handler called when an affinity instance is about to be turned on. The |
| 165 | * level and mpidr determine the affinity instance. |
| 166 | ******************************************************************************/ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 167 | int32_t tegra_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 168 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 169 | return tegra_soc_pwr_domain_on(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 173 | * Handler called when a power domain is about to be turned off. The |
| 174 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 175 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 176 | void tegra_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 177 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 178 | (void)tegra_soc_pwr_domain_off(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /******************************************************************************* |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 182 | * Handler called when a power domain is about to be suspended. The |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 183 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 184 | * This handler is called with SMP and data cache enabled, when |
| 185 | * HW_ASSISTED_COHERENCY = 0 |
| 186 | ******************************************************************************/ |
| 187 | void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
| 188 | { |
| 189 | tegra_soc_pwr_domain_suspend_pwrdown_early(target_state); |
| 190 | } |
| 191 | |
| 192 | /******************************************************************************* |
| 193 | * Handler called when a power domain is about to be suspended. The |
| 194 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 195 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 196 | void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 197 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 198 | (void)tegra_soc_pwr_domain_suspend(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 199 | |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 200 | /* Disable console if we are entering deep sleep. */ |
| 201 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 202 | PSTATE_ID_SOC_POWERDN) { |
| 203 | (void)console_uninit(); |
| 204 | } |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 205 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 206 | /* disable GICC */ |
| 207 | tegra_gic_cpuif_deactivate(); |
| 208 | } |
| 209 | |
| 210 | /******************************************************************************* |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 211 | * Handler called at the end of the power domain suspend sequence. The |
| 212 | * target_state encodes the power state that each level should transition to. |
| 213 | ******************************************************************************/ |
| 214 | __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t |
| 215 | *target_state) |
| 216 | { |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 217 | uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
| 218 | uint64_t rmr_el3 = 0; |
| 219 | |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 220 | /* call the chip's power down handler */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 221 | (void)tegra_soc_pwr_domain_power_down_wfi(target_state); |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 222 | |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 223 | /* |
| 224 | * If we are in fake system suspend mode, ensure we start doing |
| 225 | * procedures that help in looping back towards system suspend exit |
| 226 | * instead of calling WFI by requesting a warm reset. |
| 227 | * Else, just call WFI to enter low power state. |
| 228 | */ |
| 229 | if ((tegra_fake_system_suspend != 0U) && |
| 230 | (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) { |
| 231 | |
| 232 | /* warm reboot */ |
| 233 | rmr_el3 = read_rmr_el3(); |
| 234 | write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU); |
| 235 | |
| 236 | } else { |
| 237 | /* enter power down state */ |
| 238 | wfi(); |
| 239 | } |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 240 | |
| 241 | /* we can never reach here */ |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 242 | panic(); |
| 243 | } |
| 244 | |
| 245 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 246 | * Handler called when a power domain has just been powered on after |
| 247 | * being turned off earlier. The target_state encodes the low power state that |
| 248 | * each level has woken up from. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 249 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 250 | void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 251 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 252 | const plat_params_from_bl2_t *plat_params; |
Harvey Hsieh | 9e083c7 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 253 | uint32_t console_clock; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 254 | |
| 255 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 256 | * Initialize the GIC cpu and distributor interfaces |
| 257 | */ |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 258 | plat_gic_setup(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 259 | |
| 260 | /* |
| 261 | * Check if we are exiting from deep sleep. |
| 262 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 263 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 264 | PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 265 | |
Harvey Hsieh | 9e083c7 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 266 | /* |
| 267 | * Reference clock used by the FPGAs is a lot slower. |
| 268 | */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 269 | if (tegra_platform_is_fpga()) { |
Harvey Hsieh | 9e083c7 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 270 | console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; |
| 271 | } else { |
| 272 | console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; |
| 273 | } |
| 274 | |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 275 | /* Initialize the runtime console */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 276 | if (tegra_console_base != 0ULL) { |
| 277 | (void)console_init(tegra_console_base, console_clock, |
Harvey Hsieh | 9e083c7 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 278 | TEGRA_CONSOLE_BAUDRATE); |
Damon Duan | 777baa5 | 2016-11-07 19:37:50 +0800 | [diff] [blame] | 279 | } |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 280 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 281 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 282 | * Restore Memory Controller settings as it loses state |
| 283 | * during system suspend. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 284 | */ |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 285 | tegra_memctrl_restore_settings(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 286 | |
| 287 | /* |
| 288 | * Security configuration to allow DRAM/device access. |
| 289 | */ |
| 290 | plat_params = bl31_get_plat_params(); |
Varun Wadekar | 6bb6246 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 291 | tegra_memctrl_tzdram_setup(plat_params->tzdram_base, |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 292 | (uint32_t)plat_params->tzdram_size); |
Varun Wadekar | d5f578a | 2016-06-01 19:34:37 -0700 | [diff] [blame] | 293 | |
| 294 | /* |
| 295 | * Set up the TZRAM memory aperture to allow only secure world |
| 296 | * access |
| 297 | */ |
| 298 | tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | /* |
| 302 | * Reset hardware settings. |
| 303 | */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 304 | (void)tegra_soc_pwr_domain_on_finish(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 308 | * Handler called when a power domain has just been powered on after |
| 309 | * having been suspended earlier. The target_state encodes the low power state |
| 310 | * that each level has woken up from. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 311 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 312 | void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 313 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 314 | tegra_pwr_domain_on_finish(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | /******************************************************************************* |
| 318 | * Handler called when the system wants to be powered off |
| 319 | ******************************************************************************/ |
| 320 | __dead2 void tegra_system_off(void) |
| 321 | { |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 322 | INFO("Powering down system...\n"); |
| 323 | |
| 324 | tegra_soc_prepare_system_off(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | /******************************************************************************* |
| 328 | * Handler called when the system wants to be restarted. |
| 329 | ******************************************************************************/ |
| 330 | __dead2 void tegra_system_reset(void) |
| 331 | { |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 332 | INFO("Restarting system...\n"); |
| 333 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 334 | /* per-SoC system reset handler */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 335 | (void)tegra_soc_prepare_system_reset(); |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 336 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 337 | /* |
| 338 | * Program the PMC in order to restart the system. |
| 339 | */ |
| 340 | tegra_pmc_system_reset(); |
| 341 | } |
| 342 | |
| 343 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 344 | * Handler called to check the validity of the power state parameter. |
| 345 | ******************************************************************************/ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 346 | int32_t tegra_validate_power_state(uint32_t power_state, |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 347 | psci_power_state_t *req_state) |
| 348 | { |
Anthony Zhou | 4408e88 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 349 | assert(req_state != NULL); |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 350 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 351 | return tegra_soc_validate_power_state(power_state, req_state); |
| 352 | } |
| 353 | |
| 354 | /******************************************************************************* |
| 355 | * Platform handler called to check the validity of the non secure entrypoint. |
| 356 | ******************************************************************************/ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 357 | int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 358 | { |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 359 | int32_t ret = PSCI_E_INVALID_ADDRESS; |
| 360 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 361 | /* |
| 362 | * Check if the non secure entrypoint lies within the non |
| 363 | * secure DRAM. |
| 364 | */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 365 | if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) { |
| 366 | ret = PSCI_E_SUCCESS; |
| 367 | } |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 368 | |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 369 | return ret; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 373 | * Export the platform handlers to enable psci to invoke them |
| 374 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 375 | static const plat_psci_ops_t tegra_plat_psci_ops = { |
| 376 | .cpu_standby = tegra_cpu_standby, |
| 377 | .pwr_domain_on = tegra_pwr_domain_on, |
| 378 | .pwr_domain_off = tegra_pwr_domain_off, |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 379 | .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 380 | .pwr_domain_suspend = tegra_pwr_domain_suspend, |
| 381 | .pwr_domain_on_finish = tegra_pwr_domain_on_finish, |
| 382 | .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 383 | .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 384 | .system_off = tegra_system_off, |
| 385 | .system_reset = tegra_system_reset, |
| 386 | .validate_power_state = tegra_validate_power_state, |
| 387 | .validate_ns_entrypoint = tegra_validate_ns_entrypoint, |
| 388 | .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 389 | }; |
| 390 | |
| 391 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 392 | * Export the platform specific power ops and initialize Power Controller |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 393 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 394 | int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
| 395 | const plat_psci_ops_t **psci_ops) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 396 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 397 | psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; |
| 398 | |
| 399 | /* |
| 400 | * Flush entrypoint variable to PoC since it will be |
| 401 | * accessed after a reset with the caches turned off. |
| 402 | */ |
| 403 | tegra_sec_entry_point = sec_entrypoint; |
| 404 | flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); |
| 405 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 406 | /* |
| 407 | * Reset hardware settings. |
| 408 | */ |
Anthony Zhou | 85a8fa0 | 2017-03-22 14:42:42 +0800 | [diff] [blame] | 409 | (void)tegra_soc_pwr_domain_on_finish(&target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 410 | |
| 411 | /* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 412 | * Initialize PSCI ops struct |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 413 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 414 | *psci_ops = &tegra_plat_psci_ops; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 415 | |
| 416 | return 0; |
| 417 | } |
Varun Wadekar | 2497539 | 2016-05-05 14:13:30 -0700 | [diff] [blame] | 418 | |
| 419 | /******************************************************************************* |
| 420 | * Platform handler to calculate the proper target power level at the |
| 421 | * specified affinity level |
| 422 | ******************************************************************************/ |
| 423 | plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, |
| 424 | const plat_local_state_t *states, |
| 425 | unsigned int ncpu) |
| 426 | { |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 427 | return tegra_soc_get_target_pwr_state(lvl, states, ncpu); |
Varun Wadekar | 2497539 | 2016-05-05 14:13:30 -0700 | [diff] [blame] | 428 | } |