blob: ec62519f55f8f4719bc7db80d020a030a3da740a [file] [log] [blame]
Isla Mitchellea84d6b2017-08-03 16:04:46 +01001/*
Bipin Ravi86499742022-01-18 01:59:06 -06002 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
Isla Mitchellea84d6b2017-08-03 16:04:46 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
Dimitris Papastamos89736dd2018-02-13 11:28:02 +00009#include <cpuamu.h>
Isla Mitchellea84d6b2017-08-03 16:04:46 +010010#include <cpu_macros.S>
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010011#include <neoverse_n1.h>
Bipin Ravi86499742022-01-18 01:59:06 -060012#include "wa_cve_2022_23960_bhb_vector.S"
Dimitris Papastamos89736dd2018-02-13 11:28:02 +000013
John Tsichritzisfe6df392019-03-19 17:20:52 +000014/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
John Tsichritzis7557c662019-06-03 13:54:30 +010019/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
laurenw-arm94accd32019-08-20 15:51:24 -050024 .global neoverse_n1_errata_ic_trap_handler
laurenw-arm94accd32019-08-20 15:51:24 -050025
Bipin Ravi86499742022-01-18 01:59:06 -060026#if WORKAROUND_CVE_2022_23960
27 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
28#endif /* WORKAROUND_CVE_2022_23960 */
29
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010030/* --------------------------------------------------
Andre Przywarab9347402019-05-20 14:57:06 +010031 * Errata Workaround for Neoverse N1 Erratum 1043202.
John Tsichritzis56369c12019-02-19 13:49:06 +000032 * This applies to revision r0p0 and r1p0 of Neoverse N1.
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010033 * Inputs:
34 * x0: variant[4:7] and revision[0:3] of current cpu.
35 * Shall clobber: x0-x17
36 * --------------------------------------------------
37 */
John Tsichritzis56369c12019-02-19 13:49:06 +000038func errata_n1_1043202_wa
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010039 /* Compare x0 against revision r1p0 */
40 mov x17, x30
41 bl check_errata_1043202
42 cbz x0, 1f
43
44 /* Apply instruction patching sequence */
45 ldr x0, =0x0
46 msr CPUPSELR_EL3, x0
47 ldr x0, =0xF3BF8F2F
48 msr CPUPOR_EL3, x0
49 ldr x0, =0xFFFFFFFF
50 msr CPUPMR_EL3, x0
51 ldr x0, =0x800200071
52 msr CPUPCR_EL3, x0
laurenw-arm33e58f32019-08-19 11:06:18 -050053 isb
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100541:
55 ret x17
John Tsichritzis56369c12019-02-19 13:49:06 +000056endfunc errata_n1_1043202_wa
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010057
58func check_errata_1043202
59 /* Applies to r0p0 and r1p0 */
60 mov x1, #0x10
61 b cpu_rev_var_ls
62endfunc check_errata_1043202
63
Sami Mujawara8722e92019-05-10 14:28:37 +010064/* --------------------------------------------------
65 * Disable speculative loads if Neoverse N1 supports
66 * SSBS.
67 *
68 * Shall clobber: x0.
69 * --------------------------------------------------
70 */
71func neoverse_n1_disable_speculative_loads
72 /* Check if the PE implements SSBS */
73 mrs x0, id_aa64pfr1_el1
74 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
75 b.eq 1f
76
77 /* Disable speculative loads */
78 msr SSBS, xzr
Sami Mujawara8722e92019-05-10 14:28:37 +010079
801:
81 ret
82endfunc neoverse_n1_disable_speculative_loads
83
Andre Przywarab9347402019-05-20 14:57:06 +010084/* --------------------------------------------------
lauwal01bd555f42019-06-24 11:23:50 -050085 * Errata Workaround for Neoverse N1 Errata #1073348
86 * This applies to revision r0p0 and r1p0 of Neoverse N1.
87 * Inputs:
88 * x0: variant[4:7] and revision[0:3] of current cpu.
89 * Shall clobber: x0-x17
90 * --------------------------------------------------
91 */
92func errata_n1_1073348_wa
93 /* Compare x0 against revision r1p0 */
94 mov x17, x30
95 bl check_errata_1073348
96 cbz x0, 1f
97 mrs x1, NEOVERSE_N1_CPUACTLR_EL1
98 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
99 msr NEOVERSE_N1_CPUACTLR_EL1, x1
lauwal01bd555f42019-06-24 11:23:50 -05001001:
101 ret x17
102endfunc errata_n1_1073348_wa
103
104func check_errata_1073348
105 /* Applies to r0p0 and r1p0 */
106 mov x1, #0x10
107 b cpu_rev_var_ls
108endfunc check_errata_1073348
109
110/* --------------------------------------------------
lauwal01363ee3c2019-06-24 11:28:34 -0500111 * Errata Workaround for Neoverse N1 Errata #1130799
112 * This applies to revision <=r2p0 of Neoverse N1.
113 * Inputs:
114 * x0: variant[4:7] and revision[0:3] of current cpu.
115 * Shall clobber: x0-x17
116 * --------------------------------------------------
117 */
118func errata_n1_1130799_wa
119 /* Compare x0 against revision r2p0 */
120 mov x17, x30
121 bl check_errata_1130799
122 cbz x0, 1f
123 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
124 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
125 msr NEOVERSE_N1_CPUACTLR2_EL1, x1
lauwal01363ee3c2019-06-24 11:28:34 -05001261:
127 ret x17
128endfunc errata_n1_1130799_wa
129
130func check_errata_1130799
131 /* Applies to <=r2p0 */
132 mov x1, #0x20
133 b cpu_rev_var_ls
134endfunc check_errata_1130799
135
136/* --------------------------------------------------
lauwal01f2adb132019-06-24 11:32:40 -0500137 * Errata Workaround for Neoverse N1 Errata #1165347
138 * This applies to revision <=r2p0 of Neoverse N1.
139 * Inputs:
140 * x0: variant[4:7] and revision[0:3] of current cpu.
141 * Shall clobber: x0-x17
142 * --------------------------------------------------
143 */
144func errata_n1_1165347_wa
145 /* Compare x0 against revision r2p0 */
146 mov x17, x30
147 bl check_errata_1165347
148 cbz x0, 1f
149 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
150 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
151 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
152 msr NEOVERSE_N1_CPUACTLR2_EL1, x1
lauwal01f2adb132019-06-24 11:32:40 -05001531:
154 ret x17
155endfunc errata_n1_1165347_wa
156
157func check_errata_1165347
158 /* Applies to <=r2p0 */
159 mov x1, #0x20
160 b cpu_rev_var_ls
161endfunc check_errata_1165347
162
163/* --------------------------------------------------
lauwal01e1590442019-06-24 11:35:37 -0500164 * Errata Workaround for Neoverse N1 Errata #1207823
165 * This applies to revision <=r2p0 of Neoverse N1.
166 * Inputs:
167 * x0: variant[4:7] and revision[0:3] of current cpu.
168 * Shall clobber: x0-x17
169 * --------------------------------------------------
170 */
171func errata_n1_1207823_wa
172 /* Compare x0 against revision r2p0 */
173 mov x17, x30
174 bl check_errata_1207823
175 cbz x0, 1f
176 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
177 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
178 msr NEOVERSE_N1_CPUACTLR2_EL1, x1
lauwal01e1590442019-06-24 11:35:37 -05001791:
180 ret x17
181endfunc errata_n1_1207823_wa
182
183func check_errata_1207823
184 /* Applies to <=r2p0 */
185 mov x1, #0x20
186 b cpu_rev_var_ls
187endfunc check_errata_1207823
188
189/* --------------------------------------------------
lauwal01197f14c2019-06-24 11:38:53 -0500190 * Errata Workaround for Neoverse N1 Errata #1220197
191 * This applies to revision <=r2p0 of Neoverse N1.
192 * Inputs:
193 * x0: variant[4:7] and revision[0:3] of current cpu.
194 * Shall clobber: x0-x17
195 * --------------------------------------------------
196 */
197func errata_n1_1220197_wa
198 /* Compare x0 against revision r2p0 */
199 mov x17, x30
200 bl check_errata_1220197
201 cbz x0, 1f
202 mrs x1, NEOVERSE_N1_CPUECTLR_EL1
203 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
204 msr NEOVERSE_N1_CPUECTLR_EL1, x1
lauwal01197f14c2019-06-24 11:38:53 -05002051:
206 ret x17
207endfunc errata_n1_1220197_wa
208
209func check_errata_1220197
210 /* Applies to <=r2p0 */
211 mov x1, #0x20
212 b cpu_rev_var_ls
213endfunc check_errata_1220197
214
215/* --------------------------------------------------
lauwal0107c2a232019-06-24 11:42:02 -0500216 * Errata Workaround for Neoverse N1 Errata #1257314
217 * This applies to revision <=r3p0 of Neoverse N1.
218 * Inputs:
219 * x0: variant[4:7] and revision[0:3] of current cpu.
220 * Shall clobber: x0-x17
221 * --------------------------------------------------
222 */
223func errata_n1_1257314_wa
224 /* Compare x0 against revision r3p0 */
225 mov x17, x30
226 bl check_errata_1257314
227 cbz x0, 1f
228 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
229 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
230 msr NEOVERSE_N1_CPUACTLR3_EL1, x1
lauwal0107c2a232019-06-24 11:42:02 -05002311:
232 ret x17
233endfunc errata_n1_1257314_wa
234
235func check_errata_1257314
236 /* Applies to <=r3p0 */
237 mov x1, #0x30
238 b cpu_rev_var_ls
239endfunc check_errata_1257314
240
241/* --------------------------------------------------
lauwal0142771af2019-06-24 11:44:58 -0500242 * Errata Workaround for Neoverse N1 Errata #1262606
243 * This applies to revision <=r3p0 of Neoverse N1.
244 * Inputs:
245 * x0: variant[4:7] and revision[0:3] of current cpu.
246 * Shall clobber: x0-x17
247 * --------------------------------------------------
248 */
249func errata_n1_1262606_wa
250 /* Compare x0 against revision r3p0 */
251 mov x17, x30
252 bl check_errata_1262606
253 cbz x0, 1f
254 mrs x1, NEOVERSE_N1_CPUACTLR_EL1
255 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
256 msr NEOVERSE_N1_CPUACTLR_EL1, x1
lauwal0142771af2019-06-24 11:44:58 -05002571:
258 ret x17
259endfunc errata_n1_1262606_wa
260
261func check_errata_1262606
262 /* Applies to <=r3p0 */
263 mov x1, #0x30
264 b cpu_rev_var_ls
265endfunc check_errata_1262606
266
267/* --------------------------------------------------
lauwal0100396bf2019-06-24 11:47:30 -0500268 * Errata Workaround for Neoverse N1 Errata #1262888
269 * This applies to revision <=r3p0 of Neoverse N1.
270 * Inputs:
271 * x0: variant[4:7] and revision[0:3] of current cpu.
272 * Shall clobber: x0-x17
273 * --------------------------------------------------
274 */
275func errata_n1_1262888_wa
276 /* Compare x0 against revision r3p0 */
277 mov x17, x30
278 bl check_errata_1262888
279 cbz x0, 1f
280 mrs x1, NEOVERSE_N1_CPUECTLR_EL1
281 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
282 msr NEOVERSE_N1_CPUECTLR_EL1, x1
lauwal0100396bf2019-06-24 11:47:30 -05002831:
284 ret x17
285endfunc errata_n1_1262888_wa
286
287func check_errata_1262888
288 /* Applies to <=r3p0 */
289 mov x1, #0x30
290 b cpu_rev_var_ls
291endfunc check_errata_1262888
292
293/* --------------------------------------------------
lauwal01644b6ed2019-06-24 11:49:01 -0500294 * Errata Workaround for Neoverse N1 Errata #1275112
295 * This applies to revision <=r3p0 of Neoverse N1.
296 * Inputs:
297 * x0: variant[4:7] and revision[0:3] of current cpu.
298 * Shall clobber: x0-x17
299 * --------------------------------------------------
300 */
301func errata_n1_1275112_wa
302 /* Compare x0 against revision r3p0 */
303 mov x17, x30
304 bl check_errata_1275112
305 cbz x0, 1f
306 mrs x1, NEOVERSE_N1_CPUACTLR_EL1
307 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
308 msr NEOVERSE_N1_CPUACTLR_EL1, x1
lauwal01644b6ed2019-06-24 11:49:01 -05003091:
310 ret x17
311endfunc errata_n1_1275112_wa
312
313func check_errata_1275112
314 /* Applies to <=r3p0 */
315 mov x1, #0x30
316 b cpu_rev_var_ls
317endfunc check_errata_1275112
318
319/* --------------------------------------------------
Andre Przywarab9347402019-05-20 14:57:06 +0100320 * Errata Workaround for Neoverse N1 Erratum 1315703.
321 * This applies to revision <= r3p0 of Neoverse N1.
322 * Inputs:
323 * x0: variant[4:7] and revision[0:3] of current cpu.
324 * Shall clobber: x0-x17
325 * --------------------------------------------------
326 */
327func errata_n1_1315703_wa
328 /* Compare x0 against revision r3p1 */
329 mov x17, x30
330 bl check_errata_1315703
331 cbz x0, 1f
332
333 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
334 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
335 msr NEOVERSE_N1_CPUACTLR2_EL1, x0
Andre Przywarab9347402019-05-20 14:57:06 +0100336
3371:
338 ret x17
339endfunc errata_n1_1315703_wa
340
341func check_errata_1315703
342 /* Applies to everything <= r3p0. */
343 mov x1, #0x30
344 b cpu_rev_var_ls
345endfunc check_errata_1315703
346
laurenw-arm94accd32019-08-20 15:51:24 -0500347/* --------------------------------------------------
348 * Errata Workaround for Neoverse N1 Erratum 1542419.
349 * This applies to revisions r3p0 - r4p0 of Neoverse N1
350 * Inputs:
351 * x0: variant[4:7] and revision[0:3] of current cpu.
352 * Shall clobber: x0-x17
353 * --------------------------------------------------
354 */
355func errata_n1_1542419_wa
356 /* Compare x0 against revision r3p0 and r4p0 */
357 mov x17, x30
358 bl check_errata_1542419
359 cbz x0, 1f
360
laurenw-armcd9a9432019-10-11 15:45:24 -0500361 /* Apply instruction patching sequence */
laurenw-arm94accd32019-08-20 15:51:24 -0500362 ldr x0, =0x0
363 msr CPUPSELR_EL3, x0
364 ldr x0, =0xEE670D35
365 msr CPUPOR_EL3, x0
366 ldr x0, =0xFFFF0FFF
367 msr CPUPMR_EL3, x0
368 ldr x0, =0x08000020007D
369 msr CPUPCR_EL3, x0
370 isb
3711:
372 ret x17
373endfunc errata_n1_1542419_wa
374
375func check_errata_1542419
376 /* Applies to everything r3p0 - r4p0. */
377 mov x1, #0x30
378 mov x2, #0x40
379 b cpu_rev_var_range
380endfunc check_errata_1542419
381
johpow01e2428fd2020-08-05 12:27:12 -0500382 /* --------------------------------------------------
383 * Errata Workaround for Neoverse N1 Errata #1868343.
384 * This applies to revision <= r4p0 of Neoverse N1.
385 * This workaround is the same as the workaround for
386 * errata 1262606 and 1275112 but applies to a wider
387 * revision range.
388 * Inputs:
389 * x0: variant[4:7] and revision[0:3] of current cpu.
390 * Shall clobber: x0-x17
391 * --------------------------------------------------
392 */
393func errata_n1_1868343_wa
394 /*
395 * Compare x0 against revision r4p0
396 */
397 mov x17, x30
398 bl check_errata_1868343
399 cbz x0, 1f
400 mrs x1, NEOVERSE_N1_CPUACTLR_EL1
401 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
402 msr NEOVERSE_N1_CPUACTLR_EL1, x1
403 isb
4041:
405 ret x17
406endfunc errata_n1_1868343_wa
407
408func check_errata_1868343
409 /* Applies to everything <= r4p0 */
410 mov x1, #0x40
411 b cpu_rev_var_ls
412endfunc check_errata_1868343
413
johpow01f1a84f52020-10-07 14:33:15 -0500414 /* --------------------------------------------------
415 * Errata Workaround for Neoverse N1 Errata #1946160.
416 * This applies to revisions r3p0, r3p1, r4p0, and
417 * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
418 * and r2p0 but there is no fix in these revisions.
419 * Inputs:
420 * x0: variant[4:7] and revision[0:3] of current cpu.
421 * Shall clobber: x0-x17
422 * --------------------------------------------------
423 */
424func errata_n1_1946160_wa
425 /*
426 * Compare x0 against r3p0 - r4p1
427 */
428 mov x17, x30
429 bl check_errata_1946160
430 cbz x0, 1f
431
432 mov x0, #3
433 msr S3_6_C15_C8_0, x0
434 ldr x0, =0x10E3900002
435 msr S3_6_C15_C8_2, x0
436 ldr x0, =0x10FFF00083
437 msr S3_6_C15_C8_3, x0
438 ldr x0, =0x2001003FF
439 msr S3_6_C15_C8_1, x0
440
441 mov x0, #4
442 msr S3_6_C15_C8_0, x0
443 ldr x0, =0x10E3800082
444 msr S3_6_C15_C8_2, x0
445 ldr x0, =0x10FFF00083
446 msr S3_6_C15_C8_3, x0
447 ldr x0, =0x2001003FF
448 msr S3_6_C15_C8_1, x0
449
450 mov x0, #5
451 msr S3_6_C15_C8_0, x0
452 ldr x0, =0x10E3800200
453 msr S3_6_C15_C8_2, x0
454 ldr x0, =0x10FFF003E0
455 msr S3_6_C15_C8_3, x0
456 ldr x0, =0x2001003FF
457 msr S3_6_C15_C8_1, x0
458
459 isb
4601:
461 ret x17
462endfunc errata_n1_1946160_wa
463
464func check_errata_1946160
465 /* Applies to r3p0 - r4p1. */
466 mov x1, #0x30
467 mov x2, #0x41
468 b cpu_rev_var_range
469endfunc check_errata_1946160
470
Bipin Ravi9edf2492022-11-02 16:12:01 -0500471 /* ----------------------------------------------------
472 * Errata Workaround for Neoverse N1 Errata #2743102
473 * This applies to revisions <= r4p1 and is still open.
474 * x0: variant[4:7] and revision[0:3] of current cpu.
475 * Shall clobber: x0-x17
476 * ----------------------------------------------------
477 */
478func errata_n1_2743102_wa
479 mov x17, x30
480 bl check_errata_2743102
481 cbz x0, 1f
482
483 /* dsb before isb of power down sequence */
484 dsb sy
4851:
486 ret x17
487endfunc errata_n1_2743102_wa
488
489func check_errata_2743102
490 /* Applies to all revisions <= r4p1 */
491 mov x1, #0x41
492 b cpu_rev_var_ls
493endfunc check_errata_2743102
494
Bipin Ravi86499742022-01-18 01:59:06 -0600495func check_errata_cve_2022_23960
496#if WORKAROUND_CVE_2022_23960
497 mov x0, #ERRATA_APPLIES
498#else
499 mov x0, #ERRATA_MISSING
500#endif
501 ret
502endfunc check_errata_cve_2022_23960
503
John Tsichritzis56369c12019-02-19 13:49:06 +0000504func neoverse_n1_reset_func
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100505 mov x19, x30
John Tsichritzis1f9ff492019-03-04 16:41:26 +0000506
Sami Mujawara8722e92019-05-10 14:28:37 +0100507 bl neoverse_n1_disable_speculative_loads
John Tsichritzis1f9ff492019-03-04 16:41:26 +0000508
Louis Mayencourtb58142b2019-04-18 14:34:11 +0100509 /* Forces all cacheable atomic instructions to be near */
510 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
511 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
512 msr NEOVERSE_N1_CPUACTLR2_EL1, x0
513 isb
514
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100515 bl cpu_get_rev_var
516 mov x18, x0
517
John Tsichritzis56369c12019-02-19 13:49:06 +0000518#if ERRATA_N1_1043202
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100519 mov x0, x18
John Tsichritzis56369c12019-02-19 13:49:06 +0000520 bl errata_n1_1043202_wa
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100521#endif
522
lauwal01bd555f42019-06-24 11:23:50 -0500523#if ERRATA_N1_1073348
524 mov x0, x18
525 bl errata_n1_1073348_wa
526#endif
527
lauwal01363ee3c2019-06-24 11:28:34 -0500528#if ERRATA_N1_1130799
529 mov x0, x18
530 bl errata_n1_1130799_wa
531#endif
532
lauwal01f2adb132019-06-24 11:32:40 -0500533#if ERRATA_N1_1165347
534 mov x0, x18
535 bl errata_n1_1165347_wa
536#endif
537
lauwal01e1590442019-06-24 11:35:37 -0500538#if ERRATA_N1_1207823
539 mov x0, x18
540 bl errata_n1_1207823_wa
541#endif
542
lauwal01197f14c2019-06-24 11:38:53 -0500543#if ERRATA_N1_1220197
544 mov x0, x18
545 bl errata_n1_1220197_wa
546#endif
547
lauwal0107c2a232019-06-24 11:42:02 -0500548#if ERRATA_N1_1257314
549 mov x0, x18
550 bl errata_n1_1257314_wa
551#endif
552
lauwal0142771af2019-06-24 11:44:58 -0500553#if ERRATA_N1_1262606
554 mov x0, x18
555 bl errata_n1_1262606_wa
556#endif
557
lauwal0100396bf2019-06-24 11:47:30 -0500558#if ERRATA_N1_1262888
559 mov x0, x18
560 bl errata_n1_1262888_wa
561#endif
562
lauwal01644b6ed2019-06-24 11:49:01 -0500563#if ERRATA_N1_1275112
564 mov x0, x18
565 bl errata_n1_1275112_wa
566#endif
567
Andre Przywarab9347402019-05-20 14:57:06 +0100568#if ERRATA_N1_1315703
569 mov x0, x18
570 bl errata_n1_1315703_wa
571#endif
572
laurenw-arm94accd32019-08-20 15:51:24 -0500573#if ERRATA_N1_1542419
574 mov x0, x18
575 bl errata_n1_1542419_wa
576#endif
577
johpow01e2428fd2020-08-05 12:27:12 -0500578#if ERRATA_N1_1868343
579 mov x0, x18
580 bl errata_n1_1868343_wa
581#endif
582
johpow01f1a84f52020-10-07 14:33:15 -0500583#if ERRATA_N1_1946160
584 mov x0, x18
585 bl errata_n1_1946160_wa
586#endif
587
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000588#if ENABLE_AMU
589 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
590 mrs x0, actlr_el3
John Tsichritzis56369c12019-02-19 13:49:06 +0000591 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000592 msr actlr_el3, x0
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000593
594 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
595 mrs x0, actlr_el2
John Tsichritzis56369c12019-02-19 13:49:06 +0000596 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000597 msr actlr_el2, x0
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000598
599 /* Enable group0 counters */
John Tsichritzis56369c12019-02-19 13:49:06 +0000600 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000601 msr CPUAMCNTENSET_EL0, x0
Dimitris Papastamos89736dd2018-02-13 11:28:02 +0000602#endif
Louis Mayencourt8b8b13b2019-06-10 16:43:39 +0100603
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100604#if NEOVERSE_Nx_EXTERNAL_LLC
Manish Pandey3880a362020-01-24 11:54:44 +0000605 /* Some system may have External LLC, core needs to be made aware */
606 mrs x0, NEOVERSE_N1_CPUECTLR_EL1
607 orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
608 msr NEOVERSE_N1_CPUECTLR_EL1, x0
609#endif
610
Louis Mayencourt8b8b13b2019-06-10 16:43:39 +0100611#if ERRATA_DSU_936184
612 bl errata_dsu_936184_wa
613#endif
614
Bipin Ravi86499742022-01-18 01:59:06 -0600615#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
616 /*
617 * The Neoverse-N1 generic vectors are overridden to apply errata
618 * mitigation on exception entry from lower ELs.
619 */
620 adr x0, wa_cve_vbar_neoverse_n1
621 msr vbar_el3, x0
622#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
623
lauwal01cf12f262019-06-27 11:03:25 -0500624 isb
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100625 ret x19
John Tsichritzis56369c12019-02-19 13:49:06 +0000626endfunc neoverse_n1_reset_func
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100627
628 /* ---------------------------------------------
629 * HW will do the cache maintenance while powering down
630 * ---------------------------------------------
631 */
John Tsichritzis56369c12019-02-19 13:49:06 +0000632func neoverse_n1_core_pwr_dwn
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100633 /* ---------------------------------------------
634 * Enable CPU power down bit in power control register
635 * ---------------------------------------------
636 */
John Tsichritzis56369c12019-02-19 13:49:06 +0000637 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
638 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
639 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
Bipin Ravi9edf2492022-11-02 16:12:01 -0500640#if ERRATA_N1_2743102
641 mov x15, x30
642 bl cpu_get_rev_var
643 bl errata_n1_2743102_wa
644 mov x30, x15
645#endif /* ERRATA_N1_2743102 */
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100646 isb
647 ret
John Tsichritzis56369c12019-02-19 13:49:06 +0000648endfunc neoverse_n1_core_pwr_dwn
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100649
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100650#if REPORT_ERRATA
651/*
John Tsichritzis56369c12019-02-19 13:49:06 +0000652 * Errata printing function for Neoverse N1. Must follow AAPCS.
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100653 */
John Tsichritzis56369c12019-02-19 13:49:06 +0000654func neoverse_n1_errata_report
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100655 stp x8, x30, [sp, #-16]!
656
657 bl cpu_get_rev_var
658 mov x8, x0
659
660 /*
661 * Report all errata. The revision-variant information is passed to
662 * checking functions of each errata.
663 */
John Tsichritzis56369c12019-02-19 13:49:06 +0000664 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
lauwal01bd555f42019-06-24 11:23:50 -0500665 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
lauwal01363ee3c2019-06-24 11:28:34 -0500666 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
lauwal01f2adb132019-06-24 11:32:40 -0500667 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
lauwal01e1590442019-06-24 11:35:37 -0500668 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
lauwal01197f14c2019-06-24 11:38:53 -0500669 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
lauwal0107c2a232019-06-24 11:42:02 -0500670 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
lauwal0142771af2019-06-24 11:44:58 -0500671 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
lauwal0100396bf2019-06-24 11:47:30 -0500672 report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
lauwal01644b6ed2019-06-24 11:49:01 -0500673 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
Andre Przywarab9347402019-05-20 14:57:06 +0100674 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
laurenw-arm94accd32019-08-20 15:51:24 -0500675 report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
johpow01e2428fd2020-08-05 12:27:12 -0500676 report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
johpow01f1a84f52020-10-07 14:33:15 -0500677 report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
Bipin Ravi9edf2492022-11-02 16:12:01 -0500678 report_errata ERRATA_N1_2743102, neoverse_n1, 2743102
Louis Mayencourt8b8b13b2019-06-10 16:43:39 +0100679 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
Bipin Ravi86499742022-01-18 01:59:06 -0600680 report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100681
682 ldp x8, x30, [sp], #16
683 ret
John Tsichritzis56369c12019-02-19 13:49:06 +0000684endfunc neoverse_n1_errata_report
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100685#endif
laurenw-arm94accd32019-08-20 15:51:24 -0500686
687/*
688 * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
689 * inner-shareable invalidation to an arbitrary address followed by a DSB.
690 *
691 * x1: Exception Syndrome
692 */
693func neoverse_n1_errata_ic_trap_handler
694 cmp x1, #NEOVERSE_N1_EC_IC_TRAP
695 b.ne 1f
696 tlbi vae3is, xzr
697 dsb sy
698
laurenw-armcd9a9432019-10-11 15:45:24 -0500699 # Skip the IC instruction itself
700 mrs x3, elr_el3
701 add x3, x3, #4
702 msr elr_el3, x3
laurenw-arm94accd32019-08-20 15:51:24 -0500703
704 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
705 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
706 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
707 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
708
709#if IMAGE_BL31 && RAS_EXTENSION
710 /*
711 * Issue Error Synchronization Barrier to synchronize SErrors before
712 * exiting EL3. We're running with EAs unmasked, so any synchronized
713 * errors would be taken immediately; therefore no need to inspect
714 * DISR_EL1 register.
715 */
716 esb
717#endif
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800718 exception_return
laurenw-arm94accd32019-08-20 15:51:24 -05007191:
720 ret
721endfunc neoverse_n1_errata_ic_trap_handler
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100722
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100723 /* ---------------------------------------------
John Tsichritzis56369c12019-02-19 13:49:06 +0000724 * This function provides neoverse_n1 specific
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100725 * register information for crash reporting.
726 * It needs to return with x6 pointing to
727 * a list of register names in ascii and
728 * x8 - x15 having values of registers to be
729 * reported.
730 * ---------------------------------------------
731 */
John Tsichritzis56369c12019-02-19 13:49:06 +0000732.section .rodata.neoverse_n1_regs, "aS"
733neoverse_n1_regs: /* The ascii list of register names to be reported */
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100734 .asciz "cpuectlr_el1", ""
735
John Tsichritzis56369c12019-02-19 13:49:06 +0000736func neoverse_n1_cpu_reg_dump
737 adr x6, neoverse_n1_regs
738 mrs x8, NEOVERSE_N1_CPUECTLR_EL1
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100739 ret
John Tsichritzis56369c12019-02-19 13:49:06 +0000740endfunc neoverse_n1_cpu_reg_dump
Isla Mitchellea84d6b2017-08-03 16:04:46 +0100741
laurenw-arm94accd32019-08-20 15:51:24 -0500742declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
John Tsichritzis56369c12019-02-19 13:49:06 +0000743 neoverse_n1_reset_func, \
laurenw-arm94accd32019-08-20 15:51:24 -0500744 neoverse_n1_errata_ic_trap_handler, \
John Tsichritzis56369c12019-02-19 13:49:06 +0000745 neoverse_n1_core_pwr_dwn