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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
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Antonio Nino Diazf13d09a2019-01-23 21:50:09 +00007#include <drivers/arm/fvp/fvp_pwrc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <lib/bakery_lock.h>
9#include <lib/mmio.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000010#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000011#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012
Achin Gupta4f6ad662013-10-25 09:08:21 +010013/*
14 * TODO: Someday there will be a generic power controller api. At the moment
15 * each platform has its own pwrc so just exporting functions is fine.
16 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010017ARM_INSTANTIATE_LOCK;
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Soby Mathewa0fedc42016-06-16 14:52:04 +010019unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010020{
Andrew Thoelke958cc022014-06-09 12:54:15 +010021 return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
Achin Gupta4f6ad662013-10-25 09:08:21 +010022}
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Soby Mathewa0fedc42016-06-16 14:52:04 +010024unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025{
Andrew Thoelke958cc022014-06-09 12:54:15 +010026 unsigned int rc;
Dan Handley2b6b5742015-03-19 19:17:53 +000027 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010028 mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
29 rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
Dan Handley2b6b5742015-03-19 19:17:53 +000030 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010031 return rc;
32}
33
Soby Mathewa0fedc42016-06-16 14:52:04 +010034void fvp_pwrc_write_pponr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010035{
Dan Handley2b6b5742015-03-19 19:17:53 +000036 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000038 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010039}
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Soby Mathewa0fedc42016-06-16 14:52:04 +010041void fvp_pwrc_write_ppoffr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010042{
Dan Handley2b6b5742015-03-19 19:17:53 +000043 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010044 mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000045 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010046}
47
Soby Mathewa0fedc42016-06-16 14:52:04 +010048void fvp_pwrc_set_wen(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010049{
Dan Handley2b6b5742015-03-19 19:17:53 +000050 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
52 (unsigned int) (PWKUPR_WEN | mpidr));
Dan Handley2b6b5742015-03-19 19:17:53 +000053 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010054}
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Soby Mathewa0fedc42016-06-16 14:52:04 +010056void fvp_pwrc_clr_wen(u_register_t mpidr)
Achin Guptab127cdb2013-11-12 16:40:00 +000057{
Dan Handley2b6b5742015-03-19 19:17:53 +000058 arm_lock_get();
Achin Guptab127cdb2013-11-12 16:40:00 +000059 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
60 (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000061 arm_lock_release();
Achin Guptab127cdb2013-11-12 16:40:00 +000062}
63
Soby Mathewa0fedc42016-06-16 14:52:04 +010064void fvp_pwrc_write_pcoffr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010065{
Dan Handley2b6b5742015-03-19 19:17:53 +000066 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000068 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010069}
70
71/* Nothing else to do here apart from initializing the lock */
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +010072void __init plat_arm_pwrc_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010073{
Dan Handley2b6b5742015-03-19 19:17:53 +000074 arm_lock_init();
Achin Gupta4f6ad662013-10-25 09:08:21 +010075}
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