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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigiri07035432015-11-12 18:52:34 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <arch_helpers.h>
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010032#include <assert.h>
Yatharth Kochar3c0087a2016-04-14 14:49:37 +010033#include <debug.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <mmio.h>
35#include <plat_arm.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010036#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000037#include <xlat_tables.h>
38
Vikram Kanigiri07035432015-11-12 18:52:34 +000039extern const mmap_region_t plat_arm_mmap[];
Dan Handley9df48042015-03-19 18:58:55 +000040
Dan Handley9df48042015-03-19 18:58:55 +000041/* Weak definitions may be overridden in specific ARM standard platform */
42#pragma weak plat_get_ns_image_entrypoint
Vikram Kanigiri07035432015-11-12 18:52:34 +000043#pragma weak plat_arm_get_mmap
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010044
45/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
46 * conflicts with the definition in plat/common. */
47#if ERROR_DEPRECATED
48#pragma weak plat_get_syscnt_freq2
49#else
Yatharth Kochar3c0087a2016-04-14 14:49:37 +010050#pragma weak plat_get_syscnt_freq
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010051#endif
Dan Handley9df48042015-03-19 18:58:55 +000052
53/*******************************************************************************
54 * Macro generating the code for the function setting up the pagetables as per
55 * the platform memory map & initialize the mmu, for the given exception level
56 ******************************************************************************/
57#if USE_COHERENT_MEM
58#define DEFINE_CONFIGURE_MMU_EL(_el) \
59 void arm_configure_mmu_el##_el(unsigned long total_base, \
60 unsigned long total_size, \
61 unsigned long ro_start, \
62 unsigned long ro_limit, \
63 unsigned long coh_start, \
64 unsigned long coh_limit) \
65 { \
66 mmap_add_region(total_base, total_base, \
67 total_size, \
68 MT_MEMORY | MT_RW | MT_SECURE); \
69 mmap_add_region(ro_start, ro_start, \
70 ro_limit - ro_start, \
71 MT_MEMORY | MT_RO | MT_SECURE); \
72 mmap_add_region(coh_start, coh_start, \
73 coh_limit - coh_start, \
74 MT_DEVICE | MT_RW | MT_SECURE); \
Vikram Kanigiri07035432015-11-12 18:52:34 +000075 mmap_add(plat_arm_get_mmap()); \
Dan Handley9df48042015-03-19 18:58:55 +000076 init_xlat_tables(); \
77 \
78 enable_mmu_el##_el(0); \
79 }
80#else
81#define DEFINE_CONFIGURE_MMU_EL(_el) \
82 void arm_configure_mmu_el##_el(unsigned long total_base, \
83 unsigned long total_size, \
84 unsigned long ro_start, \
85 unsigned long ro_limit) \
86 { \
87 mmap_add_region(total_base, total_base, \
88 total_size, \
89 MT_MEMORY | MT_RW | MT_SECURE); \
90 mmap_add_region(ro_start, ro_start, \
91 ro_limit - ro_start, \
92 MT_MEMORY | MT_RO | MT_SECURE); \
Vikram Kanigiri07035432015-11-12 18:52:34 +000093 mmap_add(plat_arm_get_mmap()); \
Dan Handley9df48042015-03-19 18:58:55 +000094 init_xlat_tables(); \
95 \
96 enable_mmu_el##_el(0); \
97 }
98#endif
99
100/* Define EL1 and EL3 variants of the function initialising the MMU */
101DEFINE_CONFIGURE_MMU_EL(1)
102DEFINE_CONFIGURE_MMU_EL(3)
103
104
Soby Mathew21f93612016-03-23 10:11:10 +0000105uintptr_t plat_get_ns_image_entrypoint(void)
Dan Handley9df48042015-03-19 18:58:55 +0000106{
107 return PLAT_ARM_NS_IMAGE_OFFSET;
108}
109
110/*******************************************************************************
111 * Gets SPSR for BL32 entry
112 ******************************************************************************/
113uint32_t arm_get_spsr_for_bl32_entry(void)
114{
115 /*
116 * The Secure Payload Dispatcher service is responsible for
Juan Castillo7d199412015-12-14 09:35:25 +0000117 * setting the SPSR prior to entry into the BL32 image.
Dan Handley9df48042015-03-19 18:58:55 +0000118 */
119 return 0;
120}
121
122/*******************************************************************************
123 * Gets SPSR for BL33 entry
124 ******************************************************************************/
125uint32_t arm_get_spsr_for_bl33_entry(void)
126{
127 unsigned long el_status;
128 unsigned int mode;
129 uint32_t spsr;
130
131 /* Figure out what mode we enter the non-secure world in */
132 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
133 el_status &= ID_AA64PFR0_ELX_MASK;
134
135 mode = (el_status) ? MODE_EL2 : MODE_EL1;
136
137 /*
138 * TODO: Consider the possibility of specifying the SPSR in
139 * the FIP ToC and allowing the platform to have a say as
140 * well.
141 */
142 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
143 return spsr;
144}
145
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100146/*******************************************************************************
147 * Configures access to the system counter timer module.
148 ******************************************************************************/
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800149#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100150void arm_configure_sys_timer(void)
151{
152 unsigned int reg_val;
153
Juan Castilloaadf19a2015-11-06 16:02:32 +0000154#if ARM_CONFIG_CNTACR
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100155 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
156 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
157 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
158 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
Juan Castilloaadf19a2015-11-06 16:02:32 +0000159#endif /* ARM_CONFIG_CNTACR */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100160
161 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
162 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
163}
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800164#endif /* ARM_SYS_TIMCTL_BASE */
Vikram Kanigiri07035432015-11-12 18:52:34 +0000165
166/*******************************************************************************
167 * Returns ARM platform specific memory map regions.
168 ******************************************************************************/
169const mmap_region_t *plat_arm_get_mmap(void)
170{
171 return plat_arm_mmap;
172}
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100173
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100174#ifdef ARM_SYS_CNTCTL_BASE
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100175
176#if ERROR_DEPRECATED
177unsigned int plat_get_syscnt_freq2(void)
178{
Sandrine Bailleuxa8ef6652016-06-03 15:00:46 +0100179 unsigned int counter_base_frequency;
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100180#else
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100181unsigned long long plat_get_syscnt_freq(void)
182{
183 unsigned long long counter_base_frequency;
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100184#endif /* ERROR_DEPRECATED */
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100185
186 /* Read the frequency from Frequency modes table */
187 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
188
189 /* The first entry of the frequency modes table must not be 0 */
190 if (counter_base_frequency == 0)
191 panic();
192
193 return counter_base_frequency;
194}
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100195
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100196#endif /* ARM_SYS_CNTCTL_BASE */