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Antonio Nino Diaz272e8712018-09-18 01:36:00 +01001#
Carlo Caione189494a2019-08-23 18:28:36 +01002# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
Carlo Caione50e8a272019-08-23 19:34:44 +01009AML_PLAT := plat/amlogic
10AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
Carlo Caioned6e5afb2019-08-23 20:02:32 +010011AML_PLAT_COMMON := ${AML_PLAT}/common
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010012
Carlo Caione7408b0c2019-08-24 18:37:46 +010013PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
14 -I${AML_PLAT_SOC}/include \
Carlo Caione49488322019-08-24 17:28:23 +010015 -I${AML_PLAT_COMMON}/include
Carlo Caione50e8a272019-08-23 19:34:44 +010016
Carlo Caione7408b0c2019-08-24 18:37:46 +010017GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
18 drivers/arm/gic/v2/gicv2_main.c \
19 drivers/arm/gic/v2/gicv2_helpers.c \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010020 plat/common/plat_gicv2.c
21
Carlo Caione7408b0c2019-08-24 18:37:46 +010022BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
23 plat/common/plat_psci_common.c \
24 drivers/amlogic/console/aarch64/meson_console.S \
25 ${AML_PLAT_SOC}/gxbb_bl31_setup.c \
26 ${AML_PLAT_SOC}/gxbb_pm.c \
27 ${AML_PLAT_SOC}/gxbb_common.c \
Carlo Caioned6e5afb2019-08-23 20:02:32 +010028 ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
Carlo Caione7408b0c2019-08-24 18:37:46 +010029 ${AML_PLAT_COMMON}/aml_efuse.c \
30 ${AML_PLAT_COMMON}/aml_mhu.c \
31 ${AML_PLAT_COMMON}/aml_scpi.c \
32 ${AML_PLAT_COMMON}/aml_sip_svc.c \
33 ${AML_PLAT_COMMON}/aml_thermal.c \
34 ${AML_PLAT_COMMON}/aml_topology.c \
35 ${XLAT_TABLES_LIB_SRCS} \
Carlo Caione50e8a272019-08-23 19:34:44 +010036 ${GIC_SOURCES}
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010037
38# Tune compiler for Cortex-A53
39ifeq ($(notdir $(CC)),armclang)
40 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
41else ifneq ($(findstring clang,$(notdir $(CC))),)
42 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
43else
44 TF_CFLAGS_aarch64 += -mtune=cortex-a53
45endif
46
47# Build config flags
48# ------------------
49
50# Enable all errata workarounds for Cortex-A53
51ERRATA_A53_826319 := 1
52ERRATA_A53_835769 := 1
53ERRATA_A53_836870 := 1
54ERRATA_A53_843419 := 1
55ERRATA_A53_855873 := 1
56
57WORKAROUND_CVE_2017_5715 := 0
58
59# Have different sections for code and rodata
60SEPARATE_CODE_AND_RODATA := 1
61
62# Use Coherent memory
63USE_COHERENT_MEM := 1
64
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010065# Verify build config
66# -------------------
67
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010068ifneq (${RESET_TO_BL31}, 0)
Carlo Caione50e8a272019-08-23 19:34:44 +010069 $(error Error: ${PLAT} needs RESET_TO_BL31=0)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010070endif
71
72ifeq (${ARCH},aarch32)
Carlo Caione50e8a272019-08-23 19:34:44 +010073 $(error Error: AArch32 not supported on ${PLAT})
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010074endif