blob: e69f3f6316a1dfa55fbf0d7db2ea50f79ce4cd7c [file] [log] [blame]
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01001#
Carlo Caione189494a2019-08-23 18:28:36 +01002# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
Carlo Caione50e8a272019-08-23 19:34:44 +01009AML_PLAT := plat/amlogic
10AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
Carlo Caioned6e5afb2019-08-23 20:02:32 +010011AML_PLAT_COMMON := ${AML_PLAT}/common
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010012
Carlo Caione50e8a272019-08-23 19:34:44 +010013PLAT_INCLUDES := -I${AML_PLAT_SOC}/include
14
15GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010016 drivers/arm/gic/v2/gicv2_main.c \
17 drivers/arm/gic/v2/gicv2_helpers.c \
18 plat/common/plat_gicv2.c
19
Carlo Caione189494a2019-08-23 18:28:36 +010020PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \
Carlo Caione50e8a272019-08-23 19:34:44 +010021 ${AML_PLAT_SOC}/gxbb_common.c \
22 ${AML_PLAT_SOC}/gxbb_topology.c \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010023 ${XLAT_TABLES_LIB_SRCS}
24
25BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
26 plat/common/plat_psci_common.c \
Carlo Caioned6e5afb2019-08-23 20:02:32 +010027 ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
Carlo Caione50e8a272019-08-23 19:34:44 +010028 ${AML_PLAT_SOC}/gxbb_bl31_setup.c \
29 ${AML_PLAT_SOC}/gxbb_efuse.c \
30 ${AML_PLAT_SOC}/gxbb_mhu.c \
31 ${AML_PLAT_SOC}/gxbb_pm.c \
32 ${AML_PLAT_SOC}/gxbb_scpi.c \
33 ${AML_PLAT_SOC}/gxbb_sip_svc.c \
34 ${AML_PLAT_SOC}/gxbb_thermal.c \
35 ${GIC_SOURCES}
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010036
37# Tune compiler for Cortex-A53
38ifeq ($(notdir $(CC)),armclang)
39 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
40else ifneq ($(findstring clang,$(notdir $(CC))),)
41 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
42else
43 TF_CFLAGS_aarch64 += -mtune=cortex-a53
44endif
45
46# Build config flags
47# ------------------
48
49# Enable all errata workarounds for Cortex-A53
50ERRATA_A53_826319 := 1
51ERRATA_A53_835769 := 1
52ERRATA_A53_836870 := 1
53ERRATA_A53_843419 := 1
54ERRATA_A53_855873 := 1
55
56WORKAROUND_CVE_2017_5715 := 0
57
58# Have different sections for code and rodata
59SEPARATE_CODE_AND_RODATA := 1
60
61# Use Coherent memory
62USE_COHERENT_MEM := 1
63
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010064# Verify build config
65# -------------------
66
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010067ifneq (${RESET_TO_BL31}, 0)
Carlo Caione50e8a272019-08-23 19:34:44 +010068 $(error Error: ${PLAT} needs RESET_TO_BL31=0)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010069endif
70
71ifeq (${ARCH},aarch32)
Carlo Caione50e8a272019-08-23 19:34:44 +010072 $(error Error: AArch32 not supported on ${PLAT})
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010073endif