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Antonio Nino Diaz272e8712018-09-18 01:36:00 +01001#
Carlo Caione189494a2019-08-23 18:28:36 +01002# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
Carlo Caione50e8a272019-08-23 19:34:44 +01009AML_PLAT := plat/amlogic
10AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
Carlo Caioned6e5afb2019-08-23 20:02:32 +010011AML_PLAT_COMMON := ${AML_PLAT}/common
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010012
Carlo Caione7408b0c2019-08-24 18:37:46 +010013PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
14 -I${AML_PLAT_SOC}/include \
Carlo Caione49488322019-08-24 17:28:23 +010015 -I${AML_PLAT_COMMON}/include
Carlo Caione50e8a272019-08-23 19:34:44 +010016
Carlo Caione7408b0c2019-08-24 18:37:46 +010017GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
18 drivers/arm/gic/v2/gicv2_main.c \
19 drivers/arm/gic/v2/gicv2_helpers.c \
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010020 plat/common/plat_gicv2.c
21
Carlo Caione7408b0c2019-08-24 18:37:46 +010022BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
23 plat/common/plat_psci_common.c \
24 drivers/amlogic/console/aarch64/meson_console.S \
Carlo Caione4478be62019-09-18 11:03:10 +010025 ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \
26 ${AML_PLAT_SOC}/${PLAT}_pm.c \
27 ${AML_PLAT_SOC}/${PLAT}_common.c \
Carlo Caioned6e5afb2019-08-23 20:02:32 +010028 ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
Carlo Caione7408b0c2019-08-24 18:37:46 +010029 ${AML_PLAT_COMMON}/aml_efuse.c \
30 ${AML_PLAT_COMMON}/aml_mhu.c \
31 ${AML_PLAT_COMMON}/aml_scpi.c \
32 ${AML_PLAT_COMMON}/aml_sip_svc.c \
33 ${AML_PLAT_COMMON}/aml_thermal.c \
34 ${AML_PLAT_COMMON}/aml_topology.c \
Carlo Caione613bdb72019-09-05 12:27:39 +010035 ${AML_PLAT_COMMON}/aml_console.c \
Carlo Caione7408b0c2019-08-24 18:37:46 +010036 ${XLAT_TABLES_LIB_SRCS} \
Carlo Caione50e8a272019-08-23 19:34:44 +010037 ${GIC_SOURCES}
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010038
39# Tune compiler for Cortex-A53
40ifeq ($(notdir $(CC)),armclang)
41 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
42else ifneq ($(findstring clang,$(notdir $(CC))),)
43 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
44else
45 TF_CFLAGS_aarch64 += -mtune=cortex-a53
46endif
47
48# Build config flags
49# ------------------
50
51# Enable all errata workarounds for Cortex-A53
52ERRATA_A53_826319 := 1
53ERRATA_A53_835769 := 1
54ERRATA_A53_836870 := 1
55ERRATA_A53_843419 := 1
56ERRATA_A53_855873 := 1
57
58WORKAROUND_CVE_2017_5715 := 0
59
60# Have different sections for code and rodata
61SEPARATE_CODE_AND_RODATA := 1
62
63# Use Coherent memory
64USE_COHERENT_MEM := 1
65
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010066# Verify build config
67# -------------------
68
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010069ifneq (${RESET_TO_BL31}, 0)
Carlo Caione50e8a272019-08-23 19:34:44 +010070 $(error Error: ${PLAT} needs RESET_TO_BL31=0)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010071endif
72
73ifeq (${ARCH},aarch32)
Carlo Caione50e8a272019-08-23 19:34:44 +010074 $(error Error: AArch32 not supported on ${PLAT})
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010075endif