Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <arm_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 34 | #include <assert.h> |
| 35 | #include <bl_common.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 36 | #include <console.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 37 | #include <mmio.h> |
| 38 | #include <plat_arm.h> |
| 39 | #include <platform.h> |
| 40 | |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 41 | #define BL31_END (uintptr_t)(&__BL31_END__) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 42 | |
| 43 | #if USE_COHERENT_MEM |
| 44 | /* |
| 45 | * The next 2 constants identify the extents of the coherent memory region. |
| 46 | * These addresses are used by the MMU setup code and therefore they must be |
| 47 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 48 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols |
| 49 | * refer to page-aligned addresses. |
| 50 | */ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 51 | #define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__) |
| 52 | #define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 53 | #endif |
| 54 | |
| 55 | /* |
| 56 | * Placeholder variables for copying the arguments that have been passed to |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 57 | * BL31 from BL2. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 58 | */ |
| 59 | static entry_point_info_t bl32_image_ep_info; |
| 60 | static entry_point_info_t bl33_image_ep_info; |
| 61 | |
| 62 | |
| 63 | /* Weak definitions may be overridden in specific ARM standard platform */ |
| 64 | #pragma weak bl31_early_platform_setup |
| 65 | #pragma weak bl31_platform_setup |
| 66 | #pragma weak bl31_plat_arch_setup |
| 67 | #pragma weak bl31_plat_get_next_image_ep_info |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 68 | |
| 69 | |
| 70 | /******************************************************************************* |
| 71 | * Return a pointer to the 'entry_point_info' structure of the next image for the |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 72 | * security state specified. BL33 corresponds to the non-secure image type |
| 73 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 74 | * if the image does not exist. |
| 75 | ******************************************************************************/ |
| 76 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 77 | { |
| 78 | entry_point_info_t *next_image_info; |
| 79 | |
| 80 | assert(sec_state_is_valid(type)); |
| 81 | next_image_info = (type == NON_SECURE) |
| 82 | ? &bl33_image_ep_info : &bl32_image_ep_info; |
| 83 | /* |
| 84 | * None of the images on the ARM development platforms can have 0x0 |
| 85 | * as the entrypoint |
| 86 | */ |
| 87 | if (next_image_info->pc) |
| 88 | return next_image_info; |
| 89 | else |
| 90 | return NULL; |
| 91 | } |
| 92 | |
| 93 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 94 | * Perform any BL31 early platform setup common to ARM standard platforms. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 95 | * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 |
| 96 | * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be |
| 97 | * done before the MMU is initialized so that the memory layout can be used |
| 98 | * while creating page tables. BL2 has flushed this information to memory, so |
| 99 | * we are guaranteed to pick up good data. |
| 100 | ******************************************************************************/ |
| 101 | void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, |
| 102 | void *plat_params_from_bl2) |
| 103 | { |
| 104 | /* Initialize the console to provide early debug support */ |
| 105 | console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, |
| 106 | ARM_CONSOLE_BAUDRATE); |
| 107 | |
| 108 | #if RESET_TO_BL31 |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 109 | /* There are no parameters from BL2 if BL31 is a reset vector */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 110 | assert(from_bl2 == NULL); |
| 111 | assert(plat_params_from_bl2 == NULL); |
| 112 | |
Juan Castillo | 456deef | 2015-11-06 10:01:37 +0000 | [diff] [blame] | 113 | #ifdef BL32_BASE |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 114 | /* Populate entry point information for BL32 */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 115 | SET_PARAM_HEAD(&bl32_image_ep_info, |
| 116 | PARAM_EP, |
| 117 | VERSION_1, |
| 118 | 0); |
| 119 | SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); |
| 120 | bl32_image_ep_info.pc = BL32_BASE; |
| 121 | bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); |
Juan Castillo | 456deef | 2015-11-06 10:01:37 +0000 | [diff] [blame] | 122 | #endif /* BL32_BASE */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 123 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 124 | /* Populate entry point information for BL33 */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 125 | SET_PARAM_HEAD(&bl33_image_ep_info, |
| 126 | PARAM_EP, |
| 127 | VERSION_1, |
| 128 | 0); |
| 129 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 130 | * Tell BL31 where the non-trusted software image |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 131 | * is located and the entry state information |
| 132 | */ |
| 133 | bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); |
Soby Mathew | 4876ae3 | 2016-05-09 17:20:10 +0100 | [diff] [blame] | 134 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 135 | bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 136 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| 137 | |
| 138 | #else |
| 139 | /* |
| 140 | * Check params passed from BL2 should not be NULL, |
| 141 | */ |
| 142 | assert(from_bl2 != NULL); |
| 143 | assert(from_bl2->h.type == PARAM_BL31); |
| 144 | assert(from_bl2->h.version >= VERSION_1); |
| 145 | /* |
| 146 | * In debug builds, we pass a special value in 'plat_params_from_bl2' |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 147 | * to verify platform parameters from BL2 to BL31. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 148 | * In release builds, it's not used. |
| 149 | */ |
| 150 | assert(((unsigned long long)plat_params_from_bl2) == |
| 151 | ARM_BL31_PLAT_PARAM_VAL); |
| 152 | |
| 153 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 154 | * Copy BL32 (if populated by BL2) and BL33 entry point information. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 155 | * They are stored in Secure RAM, in BL2's address space. |
| 156 | */ |
Juan Castillo | 456deef | 2015-11-06 10:01:37 +0000 | [diff] [blame] | 157 | if (from_bl2->bl32_ep_info) |
| 158 | bl32_image_ep_info = *from_bl2->bl32_ep_info; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 159 | bl33_image_ep_info = *from_bl2->bl33_ep_info; |
| 160 | #endif |
| 161 | } |
| 162 | |
| 163 | void bl31_early_platform_setup(bl31_params_t *from_bl2, |
| 164 | void *plat_params_from_bl2) |
| 165 | { |
| 166 | arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); |
| 167 | |
| 168 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 169 | * Initialize Interconnect for this cluster during cold boot. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 170 | * No need for locks as no other CPU is active. |
| 171 | */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 172 | plat_arm_interconnect_init(); |
Sandrine Bailleux | da797f6 | 2015-05-14 14:13:05 +0100 | [diff] [blame] | 173 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 174 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 175 | * Enable Interconnect coherency for the primary CPU's cluster. |
Sandrine Bailleux | da797f6 | 2015-05-14 14:13:05 +0100 | [diff] [blame] | 176 | * Earlier bootloader stages might already do this (e.g. Trusted |
| 177 | * Firmware's BL1 does it) but we can't assume so. There is no harm in |
| 178 | * executing this code twice anyway. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 179 | * Platform specific PSCI code will enable coherency for other |
| 180 | * clusters. |
| 181 | */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 182 | plat_arm_interconnect_enter_coherency(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 186 | * Perform any BL31 platform setup common to ARM standard platforms |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 187 | ******************************************************************************/ |
| 188 | void arm_bl31_platform_setup(void) |
| 189 | { |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 190 | /* Initialize the GIC driver, cpu and distributor interfaces */ |
| 191 | plat_arm_gic_driver_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 192 | plat_arm_gic_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 193 | |
| 194 | #if RESET_TO_BL31 |
| 195 | /* |
| 196 | * Do initial security configuration to allow DRAM/device access |
| 197 | * (if earlier BL has not already done so). |
| 198 | */ |
| 199 | plat_arm_security_setup(); |
| 200 | |
| 201 | #endif /* RESET_TO_BL31 */ |
| 202 | |
| 203 | /* Enable and initialize the System level generic timer */ |
| 204 | mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, |
| 205 | CNTCR_FCREQ(0) | CNTCR_EN); |
| 206 | |
| 207 | /* Allow access to the System counter timer module */ |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 208 | arm_configure_sys_timer(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 209 | |
| 210 | /* Initialize power controller before setting up topology */ |
| 211 | plat_arm_pwrc_setup(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 212 | } |
| 213 | |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 214 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 215 | * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 216 | * standard platforms |
| 217 | ******************************************************************************/ |
| 218 | void arm_bl31_plat_runtime_setup(void) |
| 219 | { |
| 220 | /* Initialize the runtime console */ |
| 221 | console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, |
| 222 | ARM_CONSOLE_BAUDRATE); |
| 223 | } |
| 224 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 225 | void bl31_platform_setup(void) |
| 226 | { |
| 227 | arm_bl31_platform_setup(); |
| 228 | } |
| 229 | |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 230 | void bl31_plat_runtime_setup(void) |
| 231 | { |
| 232 | arm_bl31_plat_runtime_setup(); |
| 233 | } |
| 234 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 235 | /******************************************************************************* |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 236 | * Perform the very early platform specific architectural setup shared between |
| 237 | * ARM standard platforms. This only does basic initialization. Later |
| 238 | * architectural setup (bl31_arch_setup()) does not do anything platform |
| 239 | * specific. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 240 | ******************************************************************************/ |
| 241 | void arm_bl31_plat_arch_setup(void) |
| 242 | { |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 243 | arm_setup_page_tables(BL31_BASE, |
| 244 | BL31_END - BL31_BASE, |
| 245 | BL_CODE_BASE, |
| 246 | BL_CODE_LIMIT, |
| 247 | BL_RO_DATA_BASE, |
| 248 | BL_RO_DATA_LIMIT |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 249 | #if USE_COHERENT_MEM |
| 250 | , BL31_COHERENT_RAM_BASE, |
| 251 | BL31_COHERENT_RAM_LIMIT |
| 252 | #endif |
| 253 | ); |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 254 | enable_mmu_el3(0); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | void bl31_plat_arch_setup(void) |
| 258 | { |
| 259 | arm_bl31_plat_arch_setup(); |
| 260 | } |