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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathewea26bad2016-11-14 12:25:45 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#ifndef __CSS_DEF_H__
8#define __CSS_DEF_H__
9
10#include <arm_def.h>
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010011#include <gic_common.h>
12#include <interrupt_props.h>
Dan Handley9df48042015-03-19 18:58:55 +000013#include <tzc400.h>
14
15/*************************************************************************
16 * Definitions common to all ARM Compute SubSystems (CSS)
17 *************************************************************************/
Dan Handley9df48042015-03-19 18:58:55 +000018#define NSROM_BASE 0x1f000000
19#define NSROM_SIZE 0x00001000
20
21/* Following covers CSS Peripherals excluding NSROM and NSRAM */
22#define CSS_DEVICE_BASE 0x20000000
23#define CSS_DEVICE_SIZE 0x0e000000
Dan Handley9df48042015-03-19 18:58:55 +000024
25#define NSRAM_BASE 0x2e000000
26#define NSRAM_SIZE 0x00008000
27
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010028/* System Security Control Registers */
29#define SSC_REG_BASE 0x2a420000
30#define SSC_GPRETN (SSC_REG_BASE + 0x030)
31
Dan Handley9df48042015-03-19 18:58:55 +000032/* The slave_bootsecure controls access to GPU, DMC and CS. */
33#define CSS_NIC400_SLAVE_BOOTSECURE 8
34
35/* Interrupt handling constants */
36#define CSS_IRQ_MHU 69
37#define CSS_IRQ_GPU_SMMU_0 71
Dan Handley9df48042015-03-19 18:58:55 +000038#define CSS_IRQ_TZC 80
39#define CSS_IRQ_TZ_WDOG 86
Vikram Kanigirif3bcea22015-06-24 17:51:09 +010040#define CSS_IRQ_SEC_SYS_TIMER 91
Dan Handley9df48042015-03-19 18:58:55 +000041
Soby Mathew1ced6b82017-06-12 12:37:10 +010042/* MHU register offsets */
43#define MHU_CPU_INTR_S_SET_OFFSET 0x308
44
Sandrine Bailleux761bba32015-04-29 13:02:46 +010045/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010046 * Define a list of Group 1 Secure interrupt properties as per GICv3
47 * terminology. On a GICv2 system or mode, the interrupts will be treated as
48 * Group 0 interrupts.
Achin Gupta1fa7eb62015-11-03 14:18:34 +000049 */
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010050#define CSS_G1S_IRQ_PROPS(grp) \
51 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \
52 GIC_INTR_CFG_LEVEL), \
53 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
54 GIC_INTR_CFG_LEVEL), \
55 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \
56 GIC_INTR_CFG_LEVEL), \
57 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
58 GIC_INTR_CFG_LEVEL), \
59 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
60 GIC_INTR_CFG_LEVEL)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000061
Soby Mathew1ced6b82017-06-12 12:37:10 +010062#if CSS_USE_SCMI_SDS_DRIVER
63/* Memory region for shared data storage */
64#define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE
65#define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */
Achin Gupta1fa7eb62015-11-03 14:18:34 +000066/*
Soby Mathew1ced6b82017-06-12 12:37:10 +010067 * The SCMI Channel is placed right after the SDS region
Soby Mathewea26bad2016-11-14 12:25:45 +000068 */
Soby Mathew1ced6b82017-06-12 12:37:10 +010069#define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX)
70#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET
71
72/* Trusted mailbox base address common to all CSS */
73/* If SDS is present, then mailbox is at top of SRAM */
74#define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8)
Soby Mathewea26bad2016-11-14 12:25:45 +000075
Soby Mathew1ced6b82017-06-12 12:37:10 +010076/* Number of retries for SCP_RAM_READY flag */
77#define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */
78
79#else
Soby Mathewea26bad2016-11-14 12:25:45 +000080/*
Sandrine Bailleux761bba32015-04-29 13:02:46 +010081 * SCP <=> AP boot configuration
82 *
83 * The SCP/AP boot configuration is a 32-bit word located at a known offset from
Vikram Kanigiri72084192016-02-08 16:29:30 +000084 * the start of the Trusted SRAM.
Sandrine Bailleux761bba32015-04-29 13:02:46 +010085 *
86 * Note that the value stored at this address is only valid at boot time, before
Juan Castilloa72b6472015-12-10 15:49:17 +000087 * the SCP_BL2 image is transferred to SCP.
Sandrine Bailleux761bba32015-04-29 13:02:46 +010088 */
Vikram Kanigiri72084192016-02-08 16:29:30 +000089#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
Dan Handley9df48042015-03-19 18:58:55 +000090
Soby Mathew1ced6b82017-06-12 12:37:10 +010091/* Trusted mailbox base address common to all CSS */
92/* If SDS is not present, then the mailbox is at the bottom of SRAM */
93#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
94
95#endif /* CSS_USE_SCMI_SDS_DRIVER */
96
Dan Handley9df48042015-03-19 18:58:55 +000097#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
98 CSS_DEVICE_BASE, \
99 CSS_DEVICE_SIZE, \
100 MT_DEVICE | MT_RW | MT_SECURE)
101
Soby Mathewcbafd7a2016-11-14 12:44:32 +0000102#define CSS_MAP_NSRAM MAP_REGION_FLAT( \
103 NSRAM_BASE, \
104 NSRAM_SIZE, \
105 MT_DEVICE | MT_RW | MT_SECURE)
106
Vikram Kanigirif79d1502015-11-12 17:22:16 +0000107/* Platform ID address */
108#define SSC_VERSION_OFFSET 0x040
109
110#define SSC_VERSION_CONFIG_SHIFT 28
111#define SSC_VERSION_MAJOR_REV_SHIFT 24
112#define SSC_VERSION_MINOR_REV_SHIFT 20
113#define SSC_VERSION_DESIGNER_ID_SHIFT 12
114#define SSC_VERSION_PART_NUM_SHIFT 0x0
115#define SSC_VERSION_CONFIG_MASK 0xf
116#define SSC_VERSION_MAJOR_REV_MASK 0xf
117#define SSC_VERSION_MINOR_REV_MASK 0xf
118#define SSC_VERSION_DESIGNER_ID_MASK 0xff
119#define SSC_VERSION_PART_NUM_MASK 0xfff
120
dp-armb71946b2017-02-08 12:16:42 +0000121/* SSC debug configuration registers */
122#define SSC_DBGCFG_SET 0x14
123#define SSC_DBGCFG_CLR 0x18
124
125#define SPIDEN_INT_CLR_SHIFT 6
126#define SPIDEN_SEL_SET_SHIFT 7
127
Vikram Kanigirif79d1502015-11-12 17:22:16 +0000128#ifndef __ASSEMBLY__
129
130/* SSC_VERSION related accessors */
131
132/* Returns the part number of the platform */
133#define GET_SSC_VERSION_PART_NUM(val) \
134 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \
135 SSC_VERSION_PART_NUM_MASK)
136
137/* Returns the configuration number of the platform */
138#define GET_SSC_VERSION_CONFIG(val) \
139 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \
140 SSC_VERSION_CONFIG_MASK)
141
142#endif /* __ASSEMBLY__ */
Dan Handley9df48042015-03-19 18:58:55 +0000143
144/*************************************************************************
145 * Required platform porting definitions common to all
146 * ARM Compute SubSystems (CSS)
147 ************************************************************************/
148
149/*
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000150 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there
151 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE).
152 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load
153 * an SCP_BL2/SCP_BL2U image.
154 */
155#if CSS_LOAD_SCP_IMAGES
Soby Mathew2f6cac42017-06-13 18:00:53 +0100156
157#if ARM_BL31_IN_DRAM
158#error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config"
159#endif
160
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000161/*
Juan Castilloa72b6472015-12-10 15:49:17 +0000162 * Load address of SCP_BL2 in CSS platform ports
Soby Mathew2f6cac42017-06-13 18:00:53 +0100163 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1
164 * rw data. Once SCP_BL2 is transferred to the SCP, it is discarded and BL31
165 * is loaded over the top.
Dan Handley9df48042015-03-19 18:58:55 +0000166 */
Soby Mathew2f6cac42017-06-13 18:00:53 +0100167#define SCP_BL2_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
168#define SCP_BL2_LIMIT BL1_RW_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000169
Soby Mathew2f6cac42017-06-13 18:00:53 +0100170#define SCP_BL2U_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
171#define SCP_BL2U_LIMIT BL1_RW_BASE
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000172#endif /* CSS_LOAD_SCP_IMAGES */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100173
Dan Handley9df48042015-03-19 18:58:55 +0000174/* Load address of Non-Secure Image for CSS platform ports */
175#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
176
177/* TZC related constants */
Soby Mathew9c708b52016-02-26 14:23:19 +0000178#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
Vikram Kanigiria2cee032015-07-31 16:35:05 +0100179
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100180/*
181 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
182 * command
183 */
184#define CSS_CLUSTER_PWR_STATE_ON 0
185#define CSS_CLUSTER_PWR_STATE_OFF 3
186
187#define CSS_CPU_PWR_STATE_ON 1
188#define CSS_CPU_PWR_STATE_OFF 0
189#define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1)
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100190
Dan Handley9df48042015-03-19 18:58:55 +0000191#endif /* __CSS_DEF_H__ */