CSS: Changes for SDS framework
This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI build flag is now renamed to
`CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on
CSS platforms. Also some of the workarounds applied for SCMI are
now removed with SDS in place.
Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 9d025f6..ac0769c 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -37,6 +37,9 @@
#define CSS_IRQ_TZ_WDOG 86
#define CSS_IRQ_SEC_SYS_TIMER 91
+/* MHU register offsets */
+#define MHU_CPU_INTR_S_SET_OFFSET 0x308
+
/*
* Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a
* GICv2 system or mode, the interrupts will be treated as Group 0 interrupts.
@@ -47,17 +50,24 @@
CSS_IRQ_TZ_WDOG, \
CSS_IRQ_SEC_SYS_TIMER
+#if CSS_USE_SCMI_SDS_DRIVER
+/* Memory region for shared data storage */
+#define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE
+#define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */
/*
- * The lower Non-secure MHU channel is being used for SCMI for ARM Trusted
- * Firmware.
- * TODO: Move SCMI to Secure channel once the migration to SCMI in SCP is
- * complete.
+ * The SCMI Channel is placed right after the SDS region
*/
-#define MHU_CPU_INTR_L_SET_OFFSET 0x108
-#define MHU_CPU_INTR_H_SET_OFFSET 0x128
-#define CSS_SCMI_PAYLOAD_BASE (NSRAM_BASE + 0x500)
-#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_L_SET_OFFSET
+#define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX)
+#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET
+
+/* Trusted mailbox base address common to all CSS */
+/* If SDS is present, then mailbox is at top of SRAM */
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8)
+/* Number of retries for SCP_RAM_READY flag */
+#define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */
+
+#else
/*
* SCP <=> AP boot configuration
*
@@ -69,6 +79,12 @@
*/
#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
+/* Trusted mailbox base address common to all CSS */
+/* If SDS is not present, then the mailbox is at the bottom of SRAM */
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
+
+#endif /* CSS_USE_SCMI_SDS_DRIVER */
+
#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
CSS_DEVICE_BASE, \
CSS_DEVICE_SIZE, \
@@ -152,9 +168,6 @@
/* TZC related constants */
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
-/* Trusted mailbox base address common to all CSS */
-#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
-
/*
* Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
* command