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Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __CSS_DEF_H__
32#define __CSS_DEF_H__
33
34#include <arm_def.h>
35#include <tzc400.h>
36
37/*************************************************************************
38 * Definitions common to all ARM Compute SubSystems (CSS)
39 *************************************************************************/
Dan Handley9df48042015-03-19 18:58:55 +000040#define MHU_PAYLOAD_CACHED 0
41
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +010042#define TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
Dan Handley9df48042015-03-19 18:58:55 +000043
44#define NSROM_BASE 0x1f000000
45#define NSROM_SIZE 0x00001000
46
47/* Following covers CSS Peripherals excluding NSROM and NSRAM */
48#define CSS_DEVICE_BASE 0x20000000
49#define CSS_DEVICE_SIZE 0x0e000000
50#define MHU_BASE 0x2b1f0000
51
52#define NSRAM_BASE 0x2e000000
53#define NSRAM_SIZE 0x00008000
54
55/* The slave_bootsecure controls access to GPU, DMC and CS. */
56#define CSS_NIC400_SLAVE_BOOTSECURE 8
57
58/* Interrupt handling constants */
59#define CSS_IRQ_MHU 69
60#define CSS_IRQ_GPU_SMMU_0 71
Dan Handley9df48042015-03-19 18:58:55 +000061#define CSS_IRQ_TZC 80
62#define CSS_IRQ_TZ_WDOG 86
Vikram Kanigirif3bcea22015-06-24 17:51:09 +010063#define CSS_IRQ_SEC_SYS_TIMER 91
Dan Handley9df48042015-03-19 18:58:55 +000064
Sandrine Bailleux761bba32015-04-29 13:02:46 +010065/*
66 * SCP <=> AP boot configuration
67 *
68 * The SCP/AP boot configuration is a 32-bit word located at a known offset from
69 * the start of the Trusted SRAM. Part of this configuration is which CPU is the
70 * primary, according to the shift and mask definitions below.
71 *
72 * Note that the value stored at this address is only valid at boot time, before
73 * the BL3-0 image is transferred to SCP.
74 */
75#define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80)
Dan Handley9df48042015-03-19 18:58:55 +000076#define PRIMARY_CPU_SHIFT 8
Soby Mathew73003ac2015-05-26 16:58:54 +010077#define PRIMARY_CPU_BIT_WIDTH 4
Dan Handley9df48042015-03-19 18:58:55 +000078
Sandrine Bailleux47ea1bc2015-06-09 11:53:33 +010079/*
80 * Base address of the first memory region used for communication between AP
81 * and SCP. Used by the BOM and SCPI protocols.
82 *
83 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
84 * means the SCP/AP configuration data gets overwritten when the AP initiates
85 * communication with the SCP.
86 */
87#define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
Dan Handley9df48042015-03-19 18:58:55 +000088
89#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
90 CSS_DEVICE_BASE, \
91 CSS_DEVICE_SIZE, \
92 MT_DEVICE | MT_RW | MT_SECURE)
93
94
95/*************************************************************************
96 * Required platform porting definitions common to all
97 * ARM Compute SubSystems (CSS)
98 ************************************************************************/
99
100/*
101 * Load address of BL3-0 in CSS platform ports
102 * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
103 * SCP, it is discarded and BL3-1 is loaded over the top.
104 */
105#define BL30_BASE BL31_BASE
106
107#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED
108
109/* Load address of Non-Secure Image for CSS platform ports */
110#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
111
112/* TZC related constants */
113#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL
Vikram Kanigiricab2f5e2015-07-31 14:50:36 +0100114#define PLAT_ARM_TZC_BASE 0x2a4a0000
Dan Handley9df48042015-03-19 18:58:55 +0000115
Vikram Kanigiria2cee032015-07-31 16:35:05 +0100116/* System timer related constants */
117#define PLAT_ARM_NSTIMER_FRAME_ID 1
118
Dan Handley9df48042015-03-19 18:58:55 +0000119#endif /* __CSS_DEF_H__ */