Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Samarth Parikh | 59cfa13 | 2017-11-23 14:23:21 +0530 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 8 | #include <assert.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 9 | #include <bakery_lock.h> |
| 10 | #include <css_def.h> |
| 11 | #include <mmio.h> |
| 12 | #include <plat_arm.h> |
Soby Mathew | 200fffd | 2016-10-21 11:34:59 +0100 | [diff] [blame] | 13 | #include <platform_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 14 | #include "css_mhu.h" |
| 15 | |
| 16 | /* SCP MHU secure channel registers */ |
| 17 | #define SCP_INTR_S_STAT 0x200 |
| 18 | #define SCP_INTR_S_SET 0x208 |
| 19 | #define SCP_INTR_S_CLEAR 0x210 |
| 20 | |
| 21 | /* CPU MHU secure channel registers */ |
| 22 | #define CPU_INTR_S_STAT 0x300 |
| 23 | #define CPU_INTR_S_SET 0x308 |
| 24 | #define CPU_INTR_S_CLEAR 0x310 |
| 25 | |
Jeenu Viswambharan | 749d25b | 2017-08-23 14:12:59 +0100 | [diff] [blame] | 26 | ARM_INSTANTIATE_LOCK; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 27 | |
| 28 | /* Weak definition may be overridden in specific CSS based platform */ |
| 29 | #pragma weak plat_arm_pwrc_setup |
| 30 | |
| 31 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 32 | /* |
| 33 | * Slot 31 is reserved because the MHU hardware uses this register bit to |
| 34 | * indicate a non-secure access attempt. The total number of available slots is |
| 35 | * therefore 31 [30:0]. |
| 36 | */ |
| 37 | #define MHU_MAX_SLOT_ID 30 |
| 38 | |
| 39 | void mhu_secure_message_start(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 40 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 41 | assert(slot_id <= MHU_MAX_SLOT_ID); |
| 42 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 43 | arm_lock_get(); |
| 44 | |
| 45 | /* Make sure any previous command has finished */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 46 | while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & |
| 47 | (1 << slot_id)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 48 | ; |
| 49 | } |
| 50 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 51 | void mhu_secure_message_send(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 52 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 53 | assert(slot_id <= MHU_MAX_SLOT_ID); |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 54 | assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & |
| 55 | (1 << slot_id))); |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 56 | |
| 57 | /* Send command to SCP */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 58 | mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | uint32_t mhu_secure_message_wait(void) |
| 62 | { |
| 63 | /* Wait for response from SCP */ |
| 64 | uint32_t response; |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 65 | while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 66 | ; |
| 67 | |
| 68 | return response; |
| 69 | } |
| 70 | |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 71 | void mhu_secure_message_end(unsigned int slot_id) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | { |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 73 | assert(slot_id <= MHU_MAX_SLOT_ID); |
| 74 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 75 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 76 | * Clear any response we got by writing one in the relevant slot bit to |
| 77 | * the CLEAR register |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 78 | */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 79 | mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 80 | |
| 81 | arm_lock_release(); |
| 82 | } |
| 83 | |
| 84 | void mhu_secure_init(void) |
| 85 | { |
| 86 | arm_lock_init(); |
| 87 | |
| 88 | /* |
Sandrine Bailleux | 04b66d8 | 2015-03-18 14:52:53 +0000 | [diff] [blame] | 89 | * The STAT register resets to zero. Ensure it is in the expected state, |
| 90 | * as a stale or garbage value would make us think it's a message we've |
| 91 | * already sent. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 92 | */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 93 | assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | void plat_arm_pwrc_setup(void) |
| 97 | { |
| 98 | mhu_secure_init(); |
| 99 | } |