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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +00002 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000032#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000033#include <bakery_lock.h>
34#include <css_def.h>
35#include <mmio.h>
36#include <plat_arm.h>
Soby Mathew200fffd2016-10-21 11:34:59 +010037#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000038#include "css_mhu.h"
39
40/* SCP MHU secure channel registers */
41#define SCP_INTR_S_STAT 0x200
42#define SCP_INTR_S_SET 0x208
43#define SCP_INTR_S_CLEAR 0x210
44
45/* CPU MHU secure channel registers */
46#define CPU_INTR_S_STAT 0x300
47#define CPU_INTR_S_SET 0x308
48#define CPU_INTR_S_CLEAR 0x310
49
50ARM_INSTANTIATE_LOCK
51
52/* Weak definition may be overridden in specific CSS based platform */
53#pragma weak plat_arm_pwrc_setup
54
55
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000056/*
57 * Slot 31 is reserved because the MHU hardware uses this register bit to
58 * indicate a non-secure access attempt. The total number of available slots is
59 * therefore 31 [30:0].
60 */
61#define MHU_MAX_SLOT_ID 30
62
63void mhu_secure_message_start(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000064{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000065 assert(slot_id <= MHU_MAX_SLOT_ID);
66
Dan Handley9df48042015-03-19 18:58:55 +000067 arm_lock_get();
68
69 /* Make sure any previous command has finished */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000070 while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
71 (1 << slot_id))
Dan Handley9df48042015-03-19 18:58:55 +000072 ;
73}
74
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000075void mhu_secure_message_send(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000076{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000077 assert(slot_id <= MHU_MAX_SLOT_ID);
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000078 assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
79 (1 << slot_id)));
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000080
81 /* Send command to SCP */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000082 mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +000083}
84
85uint32_t mhu_secure_message_wait(void)
86{
87 /* Wait for response from SCP */
88 uint32_t response;
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000089 while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT)))
Dan Handley9df48042015-03-19 18:58:55 +000090 ;
91
92 return response;
93}
94
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000095void mhu_secure_message_end(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000096{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000097 assert(slot_id <= MHU_MAX_SLOT_ID);
98
Dan Handley9df48042015-03-19 18:58:55 +000099 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +0000100 * Clear any response we got by writing one in the relevant slot bit to
101 * the CLEAR register
Dan Handley9df48042015-03-19 18:58:55 +0000102 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000103 mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +0000104
105 arm_lock_release();
106}
107
108void mhu_secure_init(void)
109{
110 arm_lock_init();
111
112 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +0000113 * The STAT register resets to zero. Ensure it is in the expected state,
114 * as a stale or garbage value would make us think it's a message we've
115 * already sent.
Dan Handley9df48042015-03-19 18:58:55 +0000116 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000117 assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0);
Dan Handley9df48042015-03-19 18:58:55 +0000118}
119
120void plat_arm_pwrc_setup(void)
121{
122 mhu_secure_init();
123}