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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Samarth Parikh59cfa132017-11-23 14:23:21 +05302 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
Sandrine Bailleux04b66d82015-03-18 14:52:53 +00008#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +00009#include <bakery_lock.h>
10#include <css_def.h>
11#include <mmio.h>
12#include <plat_arm.h>
Soby Mathew200fffd2016-10-21 11:34:59 +010013#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000014#include "css_mhu.h"
15
16/* SCP MHU secure channel registers */
17#define SCP_INTR_S_STAT 0x200
18#define SCP_INTR_S_SET 0x208
19#define SCP_INTR_S_CLEAR 0x210
20
21/* CPU MHU secure channel registers */
22#define CPU_INTR_S_STAT 0x300
23#define CPU_INTR_S_SET 0x308
24#define CPU_INTR_S_CLEAR 0x310
25
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010026ARM_INSTANTIATE_LOCK;
Dan Handley9df48042015-03-19 18:58:55 +000027
28/* Weak definition may be overridden in specific CSS based platform */
29#pragma weak plat_arm_pwrc_setup
30
31
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000032/*
33 * Slot 31 is reserved because the MHU hardware uses this register bit to
34 * indicate a non-secure access attempt. The total number of available slots is
35 * therefore 31 [30:0].
36 */
37#define MHU_MAX_SLOT_ID 30
38
39void mhu_secure_message_start(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000040{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000041 assert(slot_id <= MHU_MAX_SLOT_ID);
42
Dan Handley9df48042015-03-19 18:58:55 +000043 arm_lock_get();
44
45 /* Make sure any previous command has finished */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000046 while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
47 (1 << slot_id))
Dan Handley9df48042015-03-19 18:58:55 +000048 ;
49}
50
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000051void mhu_secure_message_send(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000052{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000053 assert(slot_id <= MHU_MAX_SLOT_ID);
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000054 assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
55 (1 << slot_id)));
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000056
57 /* Send command to SCP */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000058 mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +000059}
60
61uint32_t mhu_secure_message_wait(void)
62{
63 /* Wait for response from SCP */
64 uint32_t response;
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000065 while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT)))
Dan Handley9df48042015-03-19 18:58:55 +000066 ;
67
68 return response;
69}
70
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000071void mhu_secure_message_end(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000072{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000073 assert(slot_id <= MHU_MAX_SLOT_ID);
74
Dan Handley9df48042015-03-19 18:58:55 +000075 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000076 * Clear any response we got by writing one in the relevant slot bit to
77 * the CLEAR register
Dan Handley9df48042015-03-19 18:58:55 +000078 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000079 mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +000080
81 arm_lock_release();
82}
83
84void mhu_secure_init(void)
85{
86 arm_lock_init();
87
88 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000089 * The STAT register resets to zero. Ensure it is in the expected state,
90 * as a stale or garbage value would make us think it's a message we've
91 * already sent.
Dan Handley9df48042015-03-19 18:58:55 +000092 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000093 assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0);
Dan Handley9df48042015-03-19 18:58:55 +000094}
95
96void plat_arm_pwrc_setup(void)
97{
98 mhu_secure_init();
99}