Blame - plat/nvidia/tegra/include/platform_def.h - filogic/atf

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Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	1	/*
Varun Wadekar	b513232	2017-04-10 15:30:17 -0700	[diff] [blame]	2	* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	3	*
dp-arm	fa3cf0b	2017-05-03 09:38:09 +0100	[diff] [blame]	4	* SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	5	*/
				6
Antonio Nino Diaz	5eb8837	2018-11-08 10:20:19 +0000	[diff] [blame]	7	#ifndef PLATFORM_DEF_H
				8	#define PLATFORM_DEF_H
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	9
				10	#include <arch.h>
				11	#include <common_def.h>
Varun Wadekar	a78bb1b	2015-08-07 10:03:00 +0530	[diff] [blame]	12	#include <tegra_def.h>
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	13	#include <utils_def.h>
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	14
				15	/*******************************************************************************
				16	* Generic platform constants
				17	******************************************************************************/
				18
				19	/* Size of cacheable stacks */
Masahiro Yamada	441bfdd	2016-12-25 23:36:24 +0900	[diff] [blame]	20	#ifdef IMAGE_BL31
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	21	#define PLATFORM_STACK_SIZE U(0x400)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	22	#endif
				23
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	24	#define TEGRA_PRIMARY_CPU U(0x0)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	25
Varun Wadekar	a78bb1b	2015-08-07 10:03:00 +0530	[diff] [blame]	26	#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar	88c4d22	2015-08-12 09:24:50 +0530	[diff] [blame]	27	#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
				28	PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekar	a78bb1b	2015-08-07 10:03:00 +0530	[diff] [blame]	29	#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar	88c4d22	2015-08-12 09:24:50 +0530	[diff] [blame]	30	PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	31
				32	/*******************************************************************************
				33	* Platform console related constants
				34	******************************************************************************/
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	35	#define TEGRA_CONSOLE_BAUDRATE U(115200)
				36	#define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	37
				38	/*******************************************************************************
				39	* Platform memory map related constants
				40	******************************************************************************/
				41	/* Size of trusted dram */
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	42	#define TZDRAM_SIZE U(0x00400000)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	43	#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
				44
				45	/*******************************************************************************
				46	* BL31 specific defines.
				47	******************************************************************************/
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	48	#define BL31_SIZE U(0x40000)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	49	#define BL31_BASE TZDRAM_BASE
Varun Wadekar	52a1598	2015-06-05 12:57:27 +0530	[diff] [blame]	50	#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
				51	#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
				52	#define BL32_LIMIT TZDRAM_END
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	53
				54	/*******************************************************************************
				55	* Platform specific page table and MMU setup constants
				56	******************************************************************************/
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	57	#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
				58	#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	59
				60	/*******************************************************************************
				61	* Some data must be aligned on the biggest cache line size in the platform.
				62	* This is known only to the platform as it might have a combination of
				63	* integrated and external caches.
				64	******************************************************************************/
				65	#define CACHE_WRITEBACK_SHIFT 6
Varun Wadekar	761ca73	2017-04-24 14:17:12 -0700	[diff] [blame]	66	#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
Varun Wadekar	b316e24	2015-05-19 16:48:04 +0530	[diff] [blame]	67
Antonio Nino Diaz	5eb8837	2018-11-08 10:20:19 +0000	[diff] [blame]	68	#endif /* PLATFORM_DEF_H */