blob: 76cfc0b3475f6337db085318c16f2f1df2ec16eb [file] [log] [blame]
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00001/*
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00005 */
6
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +01007#ifndef XLAT_TABLES_DEFS_H
8#define XLAT_TABLES_DEFS_H
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00009
Isla Mitchell02c63072017-07-21 14:44:36 +010010#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
12#include <lib/xlat_tables/xlat_mmu_helpers.h>
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000013
14/* Miscellaneous MMU related constants */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define NUM_2MB_IN_GB (U(1) << 9)
16#define NUM_4K_IN_2MB (U(1) << 9)
17#define NUM_GB_IN_4GB (U(1) << 2)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000018
Varun Wadekarc6a11f62017-05-25 18:04:48 -070019#define TWO_MB_SHIFT U(21)
20#define ONE_GB_SHIFT U(30)
21#define FOUR_KB_SHIFT U(12)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000022
23#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
24#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
25#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
26
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010027#define PAGE_SIZE_4KB U(4096)
28#define PAGE_SIZE_16KB U(16384)
29#define PAGE_SIZE_64KB U(65536)
30
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define INVALID_DESC U(0x0)
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010032/*
33 * A block descriptor points to a region of memory bigger than the granule size
34 * (e.g. a 2MB region when the granule size is 4KB).
35 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070036#define BLOCK_DESC U(0x1) /* Table levels 0-2 */
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010037/* A table descriptor points to the next level of translation table. */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070038#define TABLE_DESC U(0x3) /* Table levels 0-2 */
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010039/*
40 * A page descriptor points to a page, i.e. a memory region whose size is the
41 * translation granule size (e.g. 4KB).
42 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070043#define PAGE_DESC U(0x3) /* Table level 3 */
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010044
Varun Wadekarc6a11f62017-05-25 18:04:48 -070045#define DESC_MASK U(0x3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000046
47#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
48#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
49#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
50
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010051/* XN: Translation regimes that support one VA range (EL2 and EL3). */
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000052#define XN (ULL(1) << 2)
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010053/* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
54#define UXN (ULL(1) << 2)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000055#define PXN (ULL(1) << 1)
56#define CONT_HINT (ULL(1) << 0)
57#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
58
Varun Wadekarc6a11f62017-05-25 18:04:48 -070059#define NON_GLOBAL (U(1) << 9)
60#define ACCESS_FLAG (U(1) << 8)
61#define NSH (U(0x0) << 6)
62#define OSH (U(0x2) << 6)
63#define ISH (U(0x3) << 6)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000064
Julius Werner8e0ef0f2019-07-09 14:02:43 -070065#ifdef __aarch64__
Alexei Fedorov90f2e882019-05-24 12:17:09 +010066/* Guarded Page bit */
67#define GP (ULL(1) << 50)
68#endif
69
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000070#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
71
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010072/*
73 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
Antonio Nino Diaz0842bd62018-07-12 15:54:10 +010074 * 64KB. However, only 4KB are supported at the moment.
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010075 */
76#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070077#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT)
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010078#define PAGE_SIZE_MASK (PAGE_SIZE - U(1))
79#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0))
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000080
Etienne Carriereb4502772017-10-24 22:47:59 +020081#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING
82#define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */
83#else
84#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */
85#endif
Varun Wadekarc6a11f62017-05-25 18:04:48 -070086#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000087
88#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070089#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000090
Varun Wadekarc6a11f62017-05-25 18:04:48 -070091#define XLAT_TABLE_LEVEL_MAX U(3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000092
93/* Values for number of entries in each MMU translation table */
94#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070095#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010096#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - U(1))
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000097
98/* Values to convert a memory address to an index into a translation table */
99#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
100#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
101#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
102#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
103#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
104 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
105
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100106#define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level))
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000107/* Mask to get the bits used to index inside a block of a certain level */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100108#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1))
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000109/* Mask to get the address bits common to a block of a certain table level*/
110#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +0100111/*
112 * Extract from the given virtual address the index into the given lookup level.
113 * This macro assumes the system is using the 4KB translation granule.
114 */
115#define XLAT_TABLE_IDX(virtual_addr, level) \
116 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000117
118/*
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +0100119 * The ARMv8 translation table descriptor format defines AP[2:1] as the Access
120 * Permissions bits, and does not define an AP[0] bit.
121 *
122 * AP[1] is valid only for a stage 1 translation that supports two VA ranges
Antonio Nino Diaz49074492018-04-26 12:59:08 +0100123 * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). It is RES1
124 * when stage 1 translations can only support one VA range.
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000125 */
Antonio Nino Diazdcf9d922017-10-04 16:52:15 +0100126#define AP2_SHIFT U(0x7)
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100127#define AP2_RO ULL(0x1)
128#define AP2_RW ULL(0x0)
Antonio Nino Diazdcf9d922017-10-04 16:52:15 +0100129
130#define AP1_SHIFT U(0x6)
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100131#define AP1_ACCESS_UNPRIVILEGED ULL(0x1)
132#define AP1_NO_ACCESS_UNPRIVILEGED ULL(0x0)
133#define AP1_RES1 ULL(0x1)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000134
Antonio Nino Diazdcf9d922017-10-04 16:52:15 +0100135/*
136 * The following definitions must all be passed to the LOWER_ATTRS() macro to
137 * get the right bitmask.
138 */
139#define AP_RO (AP2_RO << 5)
140#define AP_RW (AP2_RW << 5)
141#define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4)
142#define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4)
Antonio Nino Diaz49074492018-04-26 12:59:08 +0100143#define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700144#define NS (U(0x1) << 3)
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100145#define ATTR_NON_CACHEABLE_INDEX ULL(0x2)
146#define ATTR_DEVICE_INDEX ULL(0x1)
147#define ATTR_IWBWA_OWBWA_NTR_INDEX ULL(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700148#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
Isla Mitchell02c63072017-07-21 14:44:36 +0100149
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000150/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
Isla Mitchell02c63072017-07-21 14:44:36 +0100151#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000152/* Device-nGnRE */
Isla Mitchell02c63072017-07-21 14:44:36 +0100153#define ATTR_DEVICE MAIR_DEV_nGnRE
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000154/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
Isla Mitchell02c63072017-07-21 14:44:36 +0100155#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000156#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700157#define ATTR_INDEX_MASK U(0x3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000158#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
159
160/*
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +0100161 * Shift values for the attributes fields in a block or page descriptor.
162 * See section D4.3.3 in the ARMv8-A ARM (issue B.a).
163 */
164
165/* Memory attributes index field, AttrIndx[2:0]. */
166#define ATTR_INDEX_SHIFT 2
167/* Non-secure bit, NS. */
168#define NS_SHIFT 5
169/* Shareability field, SH[1:0] */
170#define SHAREABILITY_SHIFT 8
171/* The Access Flag, AF. */
172#define ACCESS_FLAG_SHIFT 10
173/* The not global bit, nG. */
174#define NOT_GLOBAL_SHIFT 11
175/* Contiguous hint bit. */
176#define CONT_HINT_SHIFT 52
177/* Execute-never bits, XN. */
178#define PXN_SHIFT 53
179#define XN_SHIFT 54
180#define UXN_SHIFT XN_SHIFT
181
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000182#endif /* XLAT_TABLES_DEFS_H */