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Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00005 */
6
7#ifndef __XLAT_TABLES_DEFS_H__
8#define __XLAT_TABLES_DEFS_H__
9
Isla Mitchell02c63072017-07-21 14:44:36 +010010#include <arch.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070011#include <utils_def.h>
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000012#include <xlat_mmu_helpers.h>
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000013
14/* Miscellaneous MMU related constants */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define NUM_2MB_IN_GB (U(1) << 9)
16#define NUM_4K_IN_2MB (U(1) << 9)
17#define NUM_GB_IN_4GB (U(1) << 2)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000018
Varun Wadekarc6a11f62017-05-25 18:04:48 -070019#define TWO_MB_SHIFT U(21)
20#define ONE_GB_SHIFT U(30)
21#define FOUR_KB_SHIFT U(12)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000022
23#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
24#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
25#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
26
Varun Wadekarc6a11f62017-05-25 18:04:48 -070027#define INVALID_DESC U(0x0)
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010028/*
29 * A block descriptor points to a region of memory bigger than the granule size
30 * (e.g. a 2MB region when the granule size is 4KB).
31 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define BLOCK_DESC U(0x1) /* Table levels 0-2 */
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010033/* A table descriptor points to the next level of translation table. */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070034#define TABLE_DESC U(0x3) /* Table levels 0-2 */
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010035/*
36 * A page descriptor points to a page, i.e. a memory region whose size is the
37 * translation granule size (e.g. 4KB).
38 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070039#define PAGE_DESC U(0x3) /* Table level 3 */
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010040
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define DESC_MASK U(0x3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000042
43#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
44#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
45#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
46
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010047/* XN: Translation regimes that support one VA range (EL2 and EL3). */
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000048#define XN (ULL(1) << 2)
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010049/* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
50#define UXN (ULL(1) << 2)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000051#define PXN (ULL(1) << 1)
52#define CONT_HINT (ULL(1) << 0)
53#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
54
Varun Wadekarc6a11f62017-05-25 18:04:48 -070055#define NON_GLOBAL (U(1) << 9)
56#define ACCESS_FLAG (U(1) << 8)
57#define NSH (U(0x0) << 6)
58#define OSH (U(0x2) << 6)
59#define ISH (U(0x3) << 6)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000060
61#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
62
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010063/*
64 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
Antonio Nino Diaz0842bd62018-07-12 15:54:10 +010065 * 64KB. However, only 4KB are supported at the moment.
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010066 */
67#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070068#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000069#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
70#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
71
Varun Wadekarc6a11f62017-05-25 18:04:48 -070072#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
73#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000074
75#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070076#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000077
Varun Wadekarc6a11f62017-05-25 18:04:48 -070078#define XLAT_TABLE_LEVEL_MAX U(3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000079
80/* Values for number of entries in each MMU translation table */
81#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070082#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000083#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
84
85/* Values to convert a memory address to an index into a translation table */
86#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
87#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
88#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
89#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
90#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
91 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
92
93#define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level))
94/* Mask to get the bits used to index inside a block of a certain level */
95#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1)
96/* Mask to get the address bits common to a block of a certain table level*/
97#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +010098/*
99 * Extract from the given virtual address the index into the given lookup level.
100 * This macro assumes the system is using the 4KB translation granule.
101 */
102#define XLAT_TABLE_IDX(virtual_addr, level) \
103 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000104
105/*
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +0100106 * The ARMv8 translation table descriptor format defines AP[2:1] as the Access
107 * Permissions bits, and does not define an AP[0] bit.
108 *
109 * AP[1] is valid only for a stage 1 translation that supports two VA ranges
Antonio Nino Diaz49074492018-04-26 12:59:08 +0100110 * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). It is RES1
111 * when stage 1 translations can only support one VA range.
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000112 */
Antonio Nino Diazdcf9d922017-10-04 16:52:15 +0100113#define AP2_SHIFT U(0x7)
114#define AP2_RO U(0x1)
115#define AP2_RW U(0x0)
116
117#define AP1_SHIFT U(0x6)
118#define AP1_ACCESS_UNPRIVILEGED U(0x1)
119#define AP1_NO_ACCESS_UNPRIVILEGED U(0x0)
Antonio Nino Diaz49074492018-04-26 12:59:08 +0100120#define AP1_RES1 U(0x1)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000121
Antonio Nino Diazdcf9d922017-10-04 16:52:15 +0100122/*
123 * The following definitions must all be passed to the LOWER_ATTRS() macro to
124 * get the right bitmask.
125 */
126#define AP_RO (AP2_RO << 5)
127#define AP_RW (AP2_RW << 5)
128#define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4)
129#define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4)
Antonio Nino Diaz49074492018-04-26 12:59:08 +0100130#define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700131#define NS (U(0x1) << 3)
132#define ATTR_NON_CACHEABLE_INDEX U(0x2)
133#define ATTR_DEVICE_INDEX U(0x1)
134#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0)
135#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
Isla Mitchell02c63072017-07-21 14:44:36 +0100136
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000137/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
Isla Mitchell02c63072017-07-21 14:44:36 +0100138#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000139/* Device-nGnRE */
Isla Mitchell02c63072017-07-21 14:44:36 +0100140#define ATTR_DEVICE MAIR_DEV_nGnRE
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000141/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
Isla Mitchell02c63072017-07-21 14:44:36 +0100142#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000143#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700144#define ATTR_INDEX_MASK U(0x3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000145#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
146
147/*
Sandrine Bailleuxc3708e22017-10-13 14:17:09 +0100148 * Shift values for the attributes fields in a block or page descriptor.
149 * See section D4.3.3 in the ARMv8-A ARM (issue B.a).
150 */
151
152/* Memory attributes index field, AttrIndx[2:0]. */
153#define ATTR_INDEX_SHIFT 2
154/* Non-secure bit, NS. */
155#define NS_SHIFT 5
156/* Shareability field, SH[1:0] */
157#define SHAREABILITY_SHIFT 8
158/* The Access Flag, AF. */
159#define ACCESS_FLAG_SHIFT 10
160/* The not global bit, nG. */
161#define NOT_GLOBAL_SHIFT 11
162/* Contiguous hint bit. */
163#define CONT_HINT_SHIFT 52
164/* Execute-never bits, XN. */
165#define PXN_SHIFT 53
166#define XN_SHIFT 54
167#define UXN_SHIFT XN_SHIFT
168
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000169#endif /* __XLAT_TABLES_DEFS_H__ */