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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Zelalem Aweke4d37db82021-07-11 18:33:20 -05002# Copyright (c) 2016-2021, Arm Limited. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Alexei Fedorov132e6652020-12-07 16:38:53 +000022# ARM Architecture feature modifiers: none by default
23ARM_ARCH_FEATURE := none
24
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000025# ARM Architecture major and minor versions: 8.0 by default.
26ARM_ARCH_MAJOR := 8
27ARM_ARCH_MINOR := 0
28
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010029# Base commit to perform code check on
30BASE_COMMIT := origin/master
31
Roberto Vargase0e99462017-10-30 14:43:43 +000032# Execute BL2 at EL3
33BL2_AT_EL3 := 0
34
Balint Dobszay719ba9c2021-03-26 16:23:18 +010035# Only use SP packages if SP layout JSON is defined
36BL2_ENABLE_SP_LOAD := 0
37
Jiafei Pan43a7bf42018-03-21 07:20:09 +000038# BL2 image is stored in XIP memory, for now, this option is only supported
39# when BL2_AT_EL3 is 1.
40BL2_IN_XIP_MEM := 0
41
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080042# Do dcache invalidate upon BL2 entry at EL3
43BL2_INV_DCACHE := 1
44
Alexei Fedorov90f2e882019-05-24 12:17:09 +010045# Select the branch protection features to use.
46BRANCH_PROTECTION := 0
47
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010048# By default, consider that the platform may release several CPUs out of reset.
49# The platform Makefile is free to override this value.
50COLD_BOOT_SINGLE_CPU := 0
51
Julius Wernerb624ae02017-06-09 15:17:15 -070052# Flag to compile in coreboot support code. Exclude by default. The coreboot
53# Makefile system will set this when compiling TF as part of a coreboot image.
54COREBOOT := 0
55
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010056# For Chain of Trust
57CREATE_KEYS := 1
58
59# Build flag to include AArch32 registers in cpu context save and restore during
60# world switch. This flag must be set to 0 for AArch64-only platforms.
61CTX_INCLUDE_AARCH32_REGS := 1
62
63# Include FP registers in cpu context
64CTX_INCLUDE_FPREGS := 0
65
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000066# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
67# must be set to 1 if the platform wants to use this feature in the Secure
68# world. It is not needed to use it in the Non-secure world.
69CTX_INCLUDE_PAUTH_REGS := 0
70
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +010071# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
72# This must be set to 1 if architecture implements Nested Virtualization
73# Extension and platform wants to use this feature in the Secure world
74CTX_INCLUDE_NEVE_REGS := 0
75
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010076# Debug build
77DEBUG := 0
78
Sumit Garg392e4df2019-11-15 10:43:00 +053079# By default disable authenticated decryption support.
80DECRYPTION_SUPPORT := none
81
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010082# Build platform
83DEFAULT_PLAT := fvp
84
Christoph Müllner4f088e42019-04-24 09:45:30 +020085# Disable the generation of the binary image (ELF only).
86DISABLE_BIN_GENERATION := 0
87
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +000088# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
89# compatibility.
90DISABLE_MTPMU := 0
91
Soby Mathew9fe88042018-03-26 12:43:37 +010092# Enable capability to disable authentication dynamically. Only meant for
93# development platforms.
94DYN_DISABLE_AUTH := 0
95
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010096# Build option to enable MPAM for lower ELs
97ENABLE_MPAM_FOR_LOWER_ELS := 0
98
Soby Mathew078f1a42018-08-28 11:13:55 +010099# Flag to Enable Position Independant support (PIE)
100ENABLE_PIE := 0
101
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100102# Flag to enable Performance Measurement Framework
103ENABLE_PMF := 0
104
105# Flag to enable PSCI STATs functionality
106ENABLE_PSCI_STAT := 0
107
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500108# Flag to enable Realm Management Extension (FEAT_RME)
109ENABLE_RME := 0
110
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100111# Flag to enable runtime instrumentation using PMF
112ENABLE_RUNTIME_INSTRUMENTATION := 0
113
Douglas Raillard306593d2017-02-24 18:14:15 +0000114# Flag to enable stack corruption protection
115ENABLE_STACK_PROTECTOR := 0
116
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100117# Flag to enable exception handling in EL3
118EL3_EXCEPTION_HANDLING := 0
119
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100120# Flag to enable Branch Target Identification.
121# Internal flag not meant for direct setting.
122# Use BRANCH_PROTECTION to enable BTI.
123ENABLE_BTI := 0
124
125# Flag to enable Pointer Authentication.
126# Internal flag not meant for direct setting.
127# Use BRANCH_PROTECTION to enable PAUTH.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000128ENABLE_PAUTH := 0
129
johpow01f91e59f2021-08-04 19:38:18 -0500130# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
131ENABLE_FEAT_HCX := 0
132
Sumit Gargeec52442019-11-14 16:33:45 +0530133# By default BL31 encryption disabled
134ENCRYPT_BL31 := 0
135
136# By default BL32 encryption disabled
137ENCRYPT_BL32 := 0
138
139# Default dummy firmware encryption key
140ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
141
142# Default dummy nonce for firmware encryption
143ENC_NONCE := 1234567890abcdef12345678
144
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100145# Build flag to treat usage of deprecated platform and framework APIs as error.
146ERROR_DEPRECATED := 0
147
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000148# Fault injection support
149FAULT_INJECTION_SUPPORT := 0
150
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900151# Byte alignment that each component in FIP is aligned to
152FIP_ALIGN := 0
153
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100154# Default FIP file name
155FIP_NAME := fip.bin
156
157# Default FWU_FIP file name
158FWU_FIP_NAME := fwu_fip.bin
159
Sumit Gargeec52442019-11-14 16:33:45 +0530160# By default firmware encryption with SSK
161FW_ENC_STATUS := 0
162
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100163# For Chain of Trust
164GENERATE_COT := 0
165
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100166# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
167# default, they are for Secure EL1.
168GICV2_G0_FOR_EL3 := 0
169
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000170# Route External Aborts to EL3. Disabled by default; External Aborts are handled
171# by lower ELs.
172HANDLE_EA_EL3_FIRST := 0
173
Alexei Fedorovf11aeb72020-10-06 15:54:12 +0100174# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
175# The default value is sha256.
176HASH_ALG := sha256
177
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000178# Whether system coherency is managed in hardware, without explicit software
179# operations.
180HW_ASSISTED_COHERENCY := 0
181
Soby Mathew13b16052017-08-31 11:49:32 +0100182# Set the default algorithm for the generation of Trusted Board Boot keys
183KEY_ALG := rsa
184
Leonardo Sandoval849f7af2020-06-18 17:32:55 -0500185# Set the default key size in case KEY_ALG is rsa
186ifeq ($(KEY_ALG),rsa)
187KEY_SIZE := 2048
188endif
189
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000190# Option to build TF with Measured Boot support
191MEASURED_BOOT := 0
192
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100193# NS timer register save and restore
194NS_TIMER_SWITCH := 0
195
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800196# Include lib/libc in the final image
197OVERRIDE_LIBC := 0
198
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100199# Build PL011 UART driver in minimal generic UART mode
200PL011_GENERIC_UART := 0
201
202# By default, consider that the platform's reset address is not programmable.
203# The platform Makefile is free to override this value.
204PROGRAMMABLE_RESET_ADDRESS := 0
205
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000206# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100207PSCI_EXTENDED_STATE_ID := 0
208
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100209# Enable RAS support
210RAS_EXTENSION := 0
211
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100212# By default, BL1 acts as the reset handler, not BL31
213RESET_TO_BL31 := 0
214
215# For Chain of Trust
216SAVE_KEYS := 0
217
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100218# Software Delegated Exception support
219SDEI_SUPPORT := 0
220
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -0500221# True Random Number firmware Interface
222TRNG_SUPPORT := 0
223
Jeremy Linton90cbf522020-11-18 10:12:41 -0600224# SMCCC PCI support
225SMC_PCI_SUPPORT := 0
226
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100227# Whether code and read-only data should be put on separate memory pages. The
228# platform Makefile is free to override this value.
229SEPARATE_CODE_AND_RODATA := 0
230
Samuel Holland31a14e12018-10-17 21:40:18 -0500231# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
232# separate memory region, which may be discontiguous from the rest of BL31.
233SEPARATE_NOBITS_REGION := 0
234
Daniel Boulby468f0d72018-09-18 11:45:51 +0100235# If the BL31 image initialisation code is recalimed after use for the secondary
236# cores stack
237RECLAIM_INIT_CODE := 0
238
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100239# SPD choice
240SPD := none
241
Paul Beesleyfe975b42019-09-16 11:29:03 +0000242# Enable the Management Mode (MM)-based Secure Partition Manager implementation
243SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000244
Max Shvetsove7fd80e2020-02-25 13:55:00 +0000245# Use SPM at S-EL2 as a default config for SPMD
246SPMD_SPM_AT_SEL2 := 1
247
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100248# Flag to introduce an infinite loop in BL1 just before it exits into the next
249# image. This is meant to help debugging the post-BL2 phase.
250SPIN_ON_BL1_EXIT := 0
251
252# Flags to build TF with Trusted Boot support
253TRUSTED_BOARD_BOOT := 0
254
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100255# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100256USE_COHERENT_MEM := 1
257
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200258# Build option to add debugfs support
259USE_DEBUGFS := 0
260
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100261# Build option to fconf based io
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100262ARM_IO_IN_DTB := 0
263
264# Build option to support SDEI through fconf
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500265SDEI_IN_FCONF := 0
266
267# Build option to support Secure Interrupt descriptors through fconf
268SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100269
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100270# Build option to choose whether Trusted Firmware uses library at ROM
271USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100272
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000273# Build option to choose whether the xlat tables of BL images can be read-only.
274# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
275# which is the per BL-image option that actually enables the read-only tables
276# API. The reason for having this additional option is to have a common high
277# level makefile where we can check for incompatible features/build options.
278ALLOW_RO_XLAT_TABLES := 0
279
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100280# Chain of trust.
281COT := tbbr
282
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900283# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100284USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900285
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100286# Build verbosity
287V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100288
289# Whether to enable D-Cache early during warm boot. This is usually
290# applicable for platforms wherein interconnect programming is not
291# required to enable cache coherency after warm reset (eg: single cluster
292# platforms).
293WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100294
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100295# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100296ENABLE_SPE_FOR_LOWER_ELS := 1
297
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100298# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100299ifeq (${ARCH},aarch32)
300 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100301endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100302
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100303# Include Memory Tagging Extension registers in cpu context. This must be set
304# to 1 if the platform wants to use this feature in the Secure world and MTE is
305# enabled at ELX.
johpow01fa59c6f2020-10-02 13:41:11 -0500306CTX_INCLUDE_MTE_REGS := 0
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100307
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100308ENABLE_AMU := 0
johpow01fa59c6f2020-10-02 13:41:11 -0500309AMU_RESTRICT_COUNTERS := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100310
Max Shvetsovc4502772021-03-22 11:59:37 +0000311# By default, enable Scalable Vector Extension if implemented only for Non-secure
David Cunadoce88eee2017-10-20 11:30:57 +0100312# lower ELs
313# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
314ifneq (${ARCH},aarch32)
315 ENABLE_SVE_FOR_NS := 1
Max Shvetsovc4502772021-03-22 11:59:37 +0000316 ENABLE_SVE_FOR_SWD := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100317else
318 override ENABLE_SVE_FOR_NS := 0
Max Shvetsovc4502772021-03-22 11:59:37 +0000319 override ENABLE_SVE_FOR_SWD := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100320endif
Justin Chadwell83e04882019-08-20 11:01:52 +0100321
322SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100323
324# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
325# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
326# Default: disabled
327USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600328
329# Enable Link Time Optimization
330ENABLE_LTO := 0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000331
332# Build flag to include EL2 registers in cpu context save and restore during
333# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
334# Default is 0.
335CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000336
337# Enable Memory tag extension which is supported for architecture greater
338# than Armv8.5-A
339# By default it is set to "no"
340SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100341
342# Select workaround for AT speculative behaviour.
343ERRATA_SPECULATIVE_AT := 0
Varun Wadekar92234852020-06-12 10:11:28 -0700344
345# Trap RAS error record access from lower EL
346RAS_TRAP_LOWER_EL_ERR_ACCESS := 0
Manish V Badarkhead339892020-06-29 10:32:53 +0100347
348# Build option to create cot descriptors using fconf
349COT_DESC_IN_DTB := 0
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100350
351# Build option to provide openssl directory path
352OPENSSL_DIR := /usr
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500353
354# Build option to use the SP804 timer instead of the generic one
355USE_SP804_TIMER := 0
Manish V Badarkhe2bb45ff2021-03-16 10:01:27 +0000356
357# Build option to define number of firmware banks, used in firmware update
358# metadata structure.
359NR_OF_FW_BANKS := 2
360
361# Build option to define number of images in firmware bank, used in firmware
362# update metadata structure.
363NR_OF_IMAGES_IN_FW_BANK := 1
Manish V Badarkhe99575e42021-06-25 23:28:59 +0100364
365# Disable Firmware update support by default
366PSA_FWU_SUPPORT := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100367
368# By default, disable access of trace buffer control registers from NS
369# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
370# if FEAT_TRBE is implemented.
371# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
372# AArch32.
373ifneq (${ARCH},aarch32)
374 ENABLE_TRBE_FOR_NS := 0
375else
376 override ENABLE_TRBE_FOR_NS := 0
377endif
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100378
379# By default, disable access of trace system registers from NS lower
380# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if
381# system register trace is implemented.
382ENABLE_SYS_REG_TRACE_FOR_NS := 0
Manish V Badarkhe51a97112021-07-08 09:33:18 +0100383
384# By default, disable trace filter control registers access to NS
385# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
386# if FEAT_TRF is implemented.
387ENABLE_TRF_FOR_NS := 0