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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Ravi Patel2f34d362021-04-15 05:55:19 -07002 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
Ronak Jain11b084a2023-02-13 04:48:06 -08003 * Copyright (c) 2022-2023, Advanced Micro Devices Inc. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08006 */
7
8/* ZynqMP power management enums and defines */
9
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000010#ifndef PM_DEFS_H
11#define PM_DEFS_H
Soren Brinkmann76fcae32016-03-06 20:16:27 -080012
13/*********************************************************************
14 * Macro definitions
15 ********************************************************************/
16
17/*
18 * Version number is a 32bit value, like:
19 * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
20 */
Venkatesh Yadav Abbarapua2ca35d2022-07-04 11:40:27 +053021#define PM_VERSION_MAJOR 1U
22#define PM_VERSION_MINOR 1U
Soren Brinkmann76fcae32016-03-06 20:16:27 -080023
Venkatesh Yadav Abbarapua2ca35d2022-07-04 11:40:27 +053024#define PM_VERSION ((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080025
Ronak Jain325bad12021-12-21 01:39:59 -080026/**
27 * PM API versions
28 */
29/* Expected version of firmware APIs */
30#define FW_API_BASE_VERSION (1U)
31/* Expected version of firmware API for feature check */
32#define FW_API_VERSION_2 (2U)
33/* Version of APIs implemented in ATF */
34#define ATF_API_BASE_VERSION (1U)
Ronak Jain11b084a2023-02-13 04:48:06 -080035/* Updating the QUERY_DATA API versioning as the bitmask functionality
36 * support is added in the v2.*/
37#define TFA_API_QUERY_DATA_VERSION (2U)
Ronak Jain325bad12021-12-21 01:39:59 -080038
Soren Brinkmann76fcae32016-03-06 20:16:27 -080039/* Capabilities for RAM */
40#define PM_CAP_ACCESS 0x1U
41#define PM_CAP_CONTEXT 0x2U
42
43#define MAX_LATENCY (~0U)
44#define MAX_QOS 100U
45
Filip Drazic0bd9d0c2016-07-20 17:17:39 +020046/* State arguments of the self suspend */
47#define PM_STATE_CPU_IDLE 0x0U
48#define PM_STATE_SUSPEND_TO_RAM 0xFU
49
Ravi Patel2f34d362021-04-15 05:55:19 -070050/* APU processor states */
51#define PM_PROC_STATE_FORCEDOFF 0U
52#define PM_PROC_STATE_ACTIVE 1U
53#define PM_PROC_STATE_SLEEP 2U
54#define PM_PROC_STATE_SUSPENDING 3U
55
Ronak Jain325bad12021-12-21 01:39:59 -080056#define PM_GET_CALLBACK_DATA 0xa01
57#define PM_SET_SUSPEND_MODE 0xa02
58#define PM_GET_TRUSTZONE_VERSION 0xa03
59
Soren Brinkmann76fcae32016-03-06 20:16:27 -080060/*********************************************************************
61 * Enum definitions
62 ********************************************************************/
63
64enum pm_api_id {
65 /* Miscellaneous API functions: */
66 PM_GET_API_VERSION = 1, /* Do not change or move */
67 PM_SET_CONFIGURATION,
68 PM_GET_NODE_STATUS,
69 PM_GET_OP_CHARACTERISTIC,
70 PM_REGISTER_NOTIFIER,
71 /* API for suspending of PUs: */
72 PM_REQ_SUSPEND,
73 PM_SELF_SUSPEND,
74 PM_FORCE_POWERDOWN,
75 PM_ABORT_SUSPEND,
76 PM_REQ_WAKEUP,
77 PM_SET_WAKEUP_SOURCE,
78 PM_SYSTEM_SHUTDOWN,
79 /* API for managing PM slaves: */
80 PM_REQ_NODE,
81 PM_RELEASE_NODE,
82 PM_SET_REQUIREMENT,
83 PM_SET_MAX_LATENCY,
84 /* Direct control API functions: */
85 PM_RESET_ASSERT,
86 PM_RESET_GET_STATUS,
87 PM_MMIO_WRITE,
88 PM_MMIO_READ,
Filip Drazicca1e0af2017-03-16 16:56:53 +010089 PM_INIT_FINALIZE,
Nava kishore Manne68d460c2016-08-20 23:18:09 +053090 PM_FPGA_LOAD,
91 PM_FPGA_GET_STATUS,
Siva Durga Prasad Paladugu16427d12016-08-24 11:45:47 +053092 PM_GET_CHIPID,
Rajan Vaja670bec02018-01-18 22:54:07 -080093 PM_SECURE_RSA_AES,
94 PM_SECURE_SHA,
95 PM_SECURE_RSA,
Rajan Vaja83687612018-01-17 02:39:20 -080096 PM_PINCTRL_REQUEST,
97 PM_PINCTRL_RELEASE,
98 PM_PINCTRL_GET_FUNCTION,
99 PM_PINCTRL_SET_FUNCTION,
100 PM_PINCTRL_CONFIG_PARAM_GET,
101 PM_PINCTRL_CONFIG_PARAM_SET,
Rajan Vaja5529a012018-01-17 02:39:23 -0800102 PM_IOCTL,
Rajan Vaja35116132018-01-17 02:39:25 -0800103 /* API to query information from firmware */
104 PM_QUERY_DATA,
105 /* Clock control API functions */
106 PM_CLOCK_ENABLE,
107 PM_CLOCK_DISABLE,
108 PM_CLOCK_GETSTATE,
109 PM_CLOCK_SETDIVIDER,
110 PM_CLOCK_GETDIVIDER,
111 PM_CLOCK_SETRATE,
112 PM_CLOCK_GETRATE,
113 PM_CLOCK_SETPARENT,
114 PM_CLOCK_GETPARENT,
Siva Durga Prasad Paladugua4ed4b22018-04-30 20:06:58 +0530115 PM_SECURE_IMAGE,
Siva Durga Prasad Paladugu7c6516a2018-09-04 17:41:34 +0530116 /* FPGA PL Readback */
117 PM_FPGA_READ,
Siva Durga Prasad Paladugu8bd905b2018-09-04 18:05:50 +0530118 PM_SECURE_AES,
Jolly Shaha7cc5ee2019-01-02 12:27:00 -0800119 /* PLL control API functions */
120 PM_PLL_SET_PARAMETER,
Jolly Shahcb2f45d2019-01-04 11:28:38 -0800121 PM_PLL_GET_PARAMETER,
Jolly Shah1f0d5852019-01-04 11:32:31 -0800122 PM_PLL_SET_MODE,
Jolly Shah141421e2019-01-04 11:35:48 -0800123 PM_PLL_GET_MODE,
Kalyani Akula6ebe4832020-11-22 22:42:10 -0800124 /* PM Register Access API */
125 PM_REGISTER_ACCESS,
VNSL Durgadeb1a362020-11-23 04:46:04 -0800126 PM_EFUSE_ACCESS,
Ronak Jain325bad12021-12-21 01:39:59 -0800127 PM_FEATURE_CHECK = 63,
Nava kishore Manne0ac097f2023-02-15 16:13:48 +0530128 PM_FPGA_GET_VERSION = 72,
129 PM_FPGA_GET_FEATURE_LIST,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800130 PM_API_MAX
131};
132
133enum pm_node_id {
134 NODE_UNKNOWN = 0,
135 NODE_APU,
136 NODE_APU_0,
137 NODE_APU_1,
138 NODE_APU_2,
139 NODE_APU_3,
140 NODE_RPU,
141 NODE_RPU_0,
142 NODE_RPU_1,
Rajan Vaja670bec02018-01-18 22:54:07 -0800143 NODE_PLD,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800144 NODE_FPD,
145 NODE_OCM_BANK_0,
146 NODE_OCM_BANK_1,
147 NODE_OCM_BANK_2,
148 NODE_OCM_BANK_3,
149 NODE_TCM_0_A,
150 NODE_TCM_0_B,
151 NODE_TCM_1_A,
152 NODE_TCM_1_B,
153 NODE_L2,
154 NODE_GPU_PP_0,
155 NODE_GPU_PP_1,
156 NODE_USB_0,
157 NODE_USB_1,
158 NODE_TTC_0,
159 NODE_TTC_1,
160 NODE_TTC_2,
161 NODE_TTC_3,
162 NODE_SATA,
163 NODE_ETH_0,
164 NODE_ETH_1,
165 NODE_ETH_2,
166 NODE_ETH_3,
167 NODE_UART_0,
168 NODE_UART_1,
169 NODE_SPI_0,
170 NODE_SPI_1,
171 NODE_I2C_0,
172 NODE_I2C_1,
173 NODE_SD_0,
174 NODE_SD_1,
175 NODE_DP,
176 NODE_GDMA,
177 NODE_ADMA,
178 NODE_NAND,
179 NODE_QSPI,
180 NODE_GPIO,
181 NODE_CAN_0,
182 NODE_CAN_1,
Mirela Simonoviccd165822017-01-30 17:44:00 +0100183 NODE_EXTERN,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800184 NODE_APLL,
185 NODE_VPLL,
186 NODE_DPLL,
187 NODE_RPLL,
188 NODE_IOPLL,
189 NODE_DDR,
Mirela Simonovic0ff06ce2016-06-07 18:15:40 +0200190 NODE_IPI_APU,
Mirela Simonovic9b984be2016-06-17 16:17:23 +0200191 NODE_IPI_RPU_0,
Filip Drazic35e99e22016-07-26 12:07:05 +0200192 NODE_GPU,
193 NODE_PCIE,
194 NODE_PCAP,
195 NODE_RTC,
Rajan Vaja670bec02018-01-18 22:54:07 -0800196 NODE_LPD,
197 NODE_VCU,
198 NODE_IPI_RPU_1,
199 NODE_IPI_PL_0,
200 NODE_IPI_PL_1,
201 NODE_IPI_PL_2,
202 NODE_IPI_PL_3,
203 NODE_PL,
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800204 NODE_GEM_TSU,
205 NODE_SWDT_0,
206 NODE_SWDT_1,
207 NODE_CSU,
208 NODE_PJTAG,
209 NODE_TRACE,
210 NODE_TESTSCAN,
211 NODE_PMU,
212 NODE_MAX,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800213};
214
215enum pm_request_ack {
216 REQ_ACK_NO = 1,
217 REQ_ACK_BLOCKING,
218 REQ_ACK_NON_BLOCKING,
219};
220
221enum pm_abort_reason {
222 ABORT_REASON_WKUP_EVENT = 100,
223 ABORT_REASON_PU_BUSY,
224 ABORT_REASON_NO_PWRDN,
225 ABORT_REASON_UNKNOWN,
226};
227
228enum pm_suspend_reason {
229 SUSPEND_REASON_PU_REQ = 201,
230 SUSPEND_REASON_ALERT,
231 SUSPEND_REASON_SYS_SHUTDOWN,
232};
233
234enum pm_ram_state {
235 PM_RAM_STATE_OFF = 1,
236 PM_RAM_STATE_RETENTION,
237 PM_RAM_STATE_ON,
238};
239
240enum pm_opchar_type {
241 PM_OPCHAR_TYPE_POWER = 1,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800242 PM_OPCHAR_TYPE_TEMP,
Anes Hadziahmetagic92aee012016-05-12 16:17:30 +0200243 PM_OPCHAR_TYPE_LATENCY,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800244};
245
246/**
247 * @PM_RET_SUCCESS: success
Davorin Mista8e059012018-08-24 17:09:06 +0200248 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated)
249 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated)
Vesa Jääskeläinen28f9ce52022-04-29 08:47:24 +0300250 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled
Davorin Mista8e059012018-08-24 17:09:06 +0200251 * @PM_RET_ERROR_INTERNAL: internal error
252 * @PM_RET_ERROR_CONFLICT: conflict
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800253 * @PM_RET_ERROR_ACCESS: access rights violation
Davorin Mista8e059012018-08-24 17:09:06 +0200254 * @PM_RET_ERROR_INVALID_NODE: invalid node
255 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node
256 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800257 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
Davorin Mista8e059012018-08-24 17:09:06 +0200258 * @PM_RET_ERROR_NODE_USED: node is already in use
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800259 */
260enum pm_ret_status {
HariBabu Gattem9f9db612022-09-15 22:35:11 -0700261 PM_RET_SUCCESS = (0U),
262 PM_RET_ERROR_ARGS = (1U),
263 PM_RET_ERROR_NOTSUPPORTED = (4U),
264 PM_RET_ERROR_NOT_ENABLED = (29U),
265 PM_RET_ERROR_INTERNAL = (2000U),
266 PM_RET_ERROR_CONFLICT = (2001U),
267 PM_RET_ERROR_ACCESS = (2002U),
268 PM_RET_ERROR_INVALID_NODE = (2003U),
269 PM_RET_ERROR_DOUBLE_REQ = (2004U),
270 PM_RET_ERROR_ABORT_SUSPEND = (2005U),
271 PM_RET_ERROR_TIMEOUT = (2006U),
272 PM_RET_ERROR_NODE_USED = (2007U),
273 PM_RET_ERROR_NO_FEATURE = (2008U)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800274};
275
276/**
277 * @PM_INITIAL_BOOT: boot is a fresh system startup
278 * @PM_RESUME: boot is a resume
279 * @PM_BOOT_ERROR: error, boot cause cannot be identified
280 */
281enum pm_boot_status {
282 PM_INITIAL_BOOT,
283 PM_RESUME,
284 PM_BOOT_ERROR,
285};
286
Siva Durga Prasad Paladugu1f80d3f2018-04-30 15:56:10 +0530287/**
288 * @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown
289 * @PMF_SHUTDOWN_TYPE_RESET: reset/reboot
290 * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope
291 */
Soren Brinkmann58fbb9b2016-09-02 09:50:54 -0700292enum pm_shutdown_type {
293 PMF_SHUTDOWN_TYPE_SHUTDOWN,
294 PMF_SHUTDOWN_TYPE_RESET,
Siva Durga Prasad Paladugu1f80d3f2018-04-30 15:56:10 +0530295 PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY,
Soren Brinkmann58fbb9b2016-09-02 09:50:54 -0700296};
297
Siva Durga Prasad Paladugu1f80d3f2018-04-30 15:56:10 +0530298/**
299 * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only
300 * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL)
301 * @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system
302 */
Soren Brinkmann58fbb9b2016-09-02 09:50:54 -0700303enum pm_shutdown_subtype {
304 PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
305 PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
306 PMF_SHUTDOWN_SUBTYPE_SYSTEM,
307};
308
Jolly Shaha7cc5ee2019-01-02 12:27:00 -0800309/**
Michal Simek08341b72022-03-09 08:53:20 +0100310 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
311 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
312 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
313 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
314 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode
315 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize
316 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting
317 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control
318 * @PM_PLL_PARAM_CP: PLL charge pump control
319 * @PM_PLL_PARAM_RES: PLL loop filter resistor control
Jolly Shaha7cc5ee2019-01-02 12:27:00 -0800320 */
321enum pm_pll_param {
322 PM_PLL_PARAM_DIV2,
323 PM_PLL_PARAM_FBDIV,
324 PM_PLL_PARAM_DATA,
325 PM_PLL_PARAM_PRE_SRC,
326 PM_PLL_PARAM_POST_SRC,
327 PM_PLL_PARAM_LOCK_DLY,
328 PM_PLL_PARAM_LOCK_CNT,
329 PM_PLL_PARAM_LFHF,
330 PM_PLL_PARAM_CP,
331 PM_PLL_PARAM_RES,
332 PM_PLL_PARAM_MAX,
333};
334
Jolly Shah1f0d5852019-01-04 11:32:31 -0800335/**
Michal Simek08341b72022-03-09 08:53:20 +0100336 * @PM_PLL_MODE_RESET: PLL is in reset (not locked)
337 * @PM_PLL_MODE_INTEGER: PLL is locked in integer mode
338 * @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode
Jolly Shah1f0d5852019-01-04 11:32:31 -0800339 */
340enum pm_pll_mode {
341 PM_PLL_MODE_RESET,
342 PM_PLL_MODE_INTEGER,
343 PM_PLL_MODE_FRACTIONAL,
344 PM_PLL_MODE_MAX,
345};
Jolly Shaha7cc5ee2019-01-02 12:27:00 -0800346
Jolly Shah8b4c4c72019-01-04 11:49:46 -0800347/**
Michal Simek08341b72022-03-09 08:53:20 +0100348 * @PM_CLOCK_DIV0_ID: Clock divider 0
349 * @PM_CLOCK_DIV1_ID: Clock divider 1
Jolly Shah8b4c4c72019-01-04 11:49:46 -0800350 */
351enum pm_clock_div_id {
352 PM_CLOCK_DIV0_ID,
353 PM_CLOCK_DIV1_ID,
354};
355
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000356#endif /* PM_DEFS_H */