Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ARCH_H__ |
| 8 | #define __ARCH_H__ |
| 9 | |
Scott Branden | bf404c0 | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 10 | #include <utils_def.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 11 | |
| 12 | /******************************************************************************* |
| 13 | * MIDR bit definitions |
| 14 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 15 | #define MIDR_IMPL_MASK U(0xff) |
| 16 | #define MIDR_IMPL_SHIFT U(0x18) |
| 17 | #define MIDR_VAR_SHIFT U(20) |
| 18 | #define MIDR_VAR_BITS U(4) |
| 19 | #define MIDR_VAR_MASK U(0xf) |
| 20 | #define MIDR_REV_SHIFT U(0) |
| 21 | #define MIDR_REV_BITS U(4) |
| 22 | #define MIDR_REV_MASK U(0xf) |
| 23 | #define MIDR_PN_MASK U(0xfff) |
| 24 | #define MIDR_PN_SHIFT U(0x4) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 25 | |
| 26 | /******************************************************************************* |
| 27 | * MPIDR macros |
| 28 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 29 | #define MPIDR_MT_MASK (U(1) << 24) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 31 | #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) |
| 32 | #define MPIDR_AFFINITY_BITS U(8) |
| 33 | #define MPIDR_AFFLVL_MASK U(0xff) |
| 34 | #define MPIDR_AFF0_SHIFT U(0) |
| 35 | #define MPIDR_AFF1_SHIFT U(8) |
| 36 | #define MPIDR_AFF2_SHIFT U(16) |
| 37 | #define MPIDR_AFF3_SHIFT U(32) |
| 38 | #define MPIDR_AFFINITY_MASK U(0xff00ffffff) |
| 39 | #define MPIDR_AFFLVL_SHIFT U(3) |
| 40 | #define MPIDR_AFFLVL0 U(0) |
| 41 | #define MPIDR_AFFLVL1 U(1) |
| 42 | #define MPIDR_AFFLVL2 U(2) |
| 43 | #define MPIDR_AFFLVL3 U(3) |
Vikram Kanigiri | 4e97e54 | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 44 | #define MPIDR_AFFLVL0_VAL(mpidr) \ |
| 45 | ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) |
| 46 | #define MPIDR_AFFLVL1_VAL(mpidr) \ |
| 47 | ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) |
| 48 | #define MPIDR_AFFLVL2_VAL(mpidr) \ |
| 49 | ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) |
| 50 | #define MPIDR_AFFLVL3_VAL(mpidr) \ |
| 51 | ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) |
Soby Mathew | e2b2d8f | 2014-12-04 14:14:12 +0000 | [diff] [blame] | 52 | /* |
| 53 | * The MPIDR_MAX_AFFLVL count starts from 0. Take care to |
| 54 | * add one while using this macro to define array sizes. |
| 55 | * TODO: Support only the first 3 affinity levels for now. |
| 56 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 57 | #define MPIDR_MAX_AFFLVL U(2) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | |
| 59 | /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 60 | #define FIRST_MPIDR U(0) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 61 | |
| 62 | /******************************************************************************* |
Andrew Thoelke | 3f78dc3 | 2014-06-02 15:44:43 +0100 | [diff] [blame] | 63 | * Definitions for CPU system register interface to GICv3 |
| 64 | ******************************************************************************/ |
| 65 | #define ICC_SRE_EL1 S3_0_C12_C12_5 |
| 66 | #define ICC_SRE_EL2 S3_4_C12_C9_5 |
| 67 | #define ICC_SRE_EL3 S3_6_C12_C12_5 |
| 68 | #define ICC_CTLR_EL1 S3_0_C12_C12_4 |
| 69 | #define ICC_CTLR_EL3 S3_6_C12_C12_4 |
| 70 | #define ICC_PMR_EL1 S3_0_C4_C6_0 |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 71 | #define ICC_RPR_EL1 S3_0_C12_C11_3 |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 72 | #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 |
| 73 | #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 |
| 74 | #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 |
| 75 | #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 |
| 76 | #define ICC_IAR0_EL1 S3_0_c12_c8_0 |
| 77 | #define ICC_IAR1_EL1 S3_0_c12_c12_0 |
| 78 | #define ICC_EOIR0_EL1 S3_0_c12_c8_1 |
| 79 | #define ICC_EOIR1_EL1 S3_0_c12_c12_1 |
Jeenu Viswambharan | ab14e9b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 80 | #define ICC_SGI0R_EL1 S3_0_c12_c11_7 |
Andrew Thoelke | 3f78dc3 | 2014-06-02 15:44:43 +0100 | [diff] [blame] | 81 | |
| 82 | /******************************************************************************* |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 83 | * Generic timer memory mapped registers & offsets |
| 84 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 85 | #define CNTCR_OFF U(0x000) |
| 86 | #define CNTFID_OFF U(0x020) |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 87 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 88 | #define CNTCR_EN (U(1) << 0) |
| 89 | #define CNTCR_HDBG (U(1) << 1) |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 90 | #define CNTCR_FCREQ(x) ((x) << 8) |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 91 | |
| 92 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | * System register bit definitions |
| 94 | ******************************************************************************/ |
| 95 | /* CLIDR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 96 | #define LOUIS_SHIFT U(21) |
| 97 | #define LOC_SHIFT U(24) |
| 98 | #define CLIDR_FIELD_WIDTH U(3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 99 | |
| 100 | /* CSSELR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 101 | #define LEVEL_SHIFT U(1) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 102 | |
| 103 | /* D$ set/way op type defines */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 104 | #define DCISW U(0x0) |
| 105 | #define DCCISW U(0x1) |
| 106 | #define DCCSW U(0x2) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 107 | |
| 108 | /* ID_AA64PFR0_EL1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 109 | #define ID_AA64PFR0_EL0_SHIFT U(0) |
| 110 | #define ID_AA64PFR0_EL1_SHIFT U(4) |
| 111 | #define ID_AA64PFR0_EL2_SHIFT U(8) |
| 112 | #define ID_AA64PFR0_EL3_SHIFT U(12) |
| 113 | #define ID_AA64PFR0_ELX_MASK U(0xf) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 114 | |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 115 | /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ |
| 116 | #define ID_AA64DFR0_PMS_SHIFT U(32) |
| 117 | #define ID_AA64DFR0_PMS_LENGTH U(4) |
| 118 | #define ID_AA64DFR0_PMS_MASK U(0xf) |
| 119 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 120 | #define EL_IMPL_NONE U(0) |
| 121 | #define EL_IMPL_A64ONLY U(1) |
| 122 | #define EL_IMPL_A64_A32 U(2) |
Jeenu Viswambharan | 2a9b882 | 2017-02-21 14:40:44 +0000 | [diff] [blame] | 123 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 124 | #define ID_AA64PFR0_GIC_SHIFT U(24) |
| 125 | #define ID_AA64PFR0_GIC_WIDTH U(4) |
| 126 | #define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1) |
Achin Gupta | 92712a5 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 127 | |
Antonio Nino Diaz | d1beee2 | 2016-12-13 15:28:54 +0000 | [diff] [blame] | 128 | /* ID_AA64MMFR0_EL1 definitions */ |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 129 | #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 130 | #define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf) |
Antonio Nino Diaz | d1beee2 | 2016-12-13 15:28:54 +0000 | [diff] [blame] | 131 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 132 | #define PARANGE_0000 U(32) |
| 133 | #define PARANGE_0001 U(36) |
| 134 | #define PARANGE_0010 U(40) |
| 135 | #define PARANGE_0011 U(42) |
| 136 | #define PARANGE_0100 U(44) |
| 137 | #define PARANGE_0101 U(48) |
Antonio Nino Diaz | d1beee2 | 2016-12-13 15:28:54 +0000 | [diff] [blame] | 138 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 139 | #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) |
| 140 | #define ID_AA64MMFR0_EL1_TGRAN4_MASK U(0xf) |
| 141 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED U(0x0) |
| 142 | #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED U(0xf) |
| 143 | |
| 144 | #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) |
| 145 | #define ID_AA64MMFR0_EL1_TGRAN64_MASK U(0xf) |
| 146 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED U(0x0) |
| 147 | #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED U(0xf) |
| 148 | |
| 149 | #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) |
| 150 | #define ID_AA64MMFR0_EL1_TGRAN16_MASK U(0xf) |
| 151 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED U(0x1) |
| 152 | #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED U(0x0) |
| 153 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | /* ID_PFR1_EL1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 155 | #define ID_PFR1_VIRTEXT_SHIFT U(12) |
| 156 | #define ID_PFR1_VIRTEXT_MASK U(0xf) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 157 | #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ |
| 158 | & ID_PFR1_VIRTEXT_MASK) |
| 159 | |
| 160 | /* SCTLR definitions */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 161 | #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 162 | (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ |
| 163 | (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 164 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 165 | #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 166 | (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) |
Jens Wiklander | c93c9df | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 167 | #define SCTLR_AARCH32_EL1_RES1 \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 168 | ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ |
| 169 | (U(1) << 4) | (U(1) << 3)) |
Jens Wiklander | c93c9df | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 170 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 171 | #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
| 172 | (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ |
| 173 | (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) |
| 174 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 175 | #define SCTLR_M_BIT (U(1) << 0) |
| 176 | #define SCTLR_A_BIT (U(1) << 1) |
| 177 | #define SCTLR_C_BIT (U(1) << 2) |
| 178 | #define SCTLR_SA_BIT (U(1) << 3) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 179 | #define SCTLR_SA0_BIT (U(1) << 4) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 180 | #define SCTLR_CP15BEN_BIT (U(1) << 5) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 181 | #define SCTLR_ITD_BIT (U(1) << 7) |
| 182 | #define SCTLR_SED_BIT (U(1) << 8) |
| 183 | #define SCTLR_UMA_BIT (U(1) << 9) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 184 | #define SCTLR_I_BIT (U(1) << 12) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 185 | #define SCTLR_V_BIT (U(1) << 13) |
| 186 | #define SCTLR_DZE_BIT (U(1) << 14) |
| 187 | #define SCTLR_UCT_BIT (U(1) << 15) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 188 | #define SCTLR_NTWI_BIT (U(1) << 16) |
| 189 | #define SCTLR_NTWE_BIT (U(1) << 18) |
| 190 | #define SCTLR_WXN_BIT (U(1) << 19) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 191 | #define SCTLR_UWXN_BIT (U(1) << 20) |
| 192 | #define SCTLR_E0E_BIT (U(1) << 24) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 193 | #define SCTLR_EE_BIT (U(1) << 25) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 194 | #define SCTLR_UCI_BIT (U(1) << 26) |
| 195 | #define SCTLR_TRE_BIT (U(1) << 28) |
| 196 | #define SCTLR_AFE_BIT (U(1) << 29) |
| 197 | #define SCTLR_TE_BIT (U(1) << 30) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 198 | #define SCTLR_RESET_VAL SCTLR_EL3_RES1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 199 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 200 | /* CPACR_El1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 201 | #define CPACR_EL1_FPEN(x) ((x) << 20) |
| 202 | #define CPACR_EL1_FP_TRAP_EL0 U(0x1) |
| 203 | #define CPACR_EL1_FP_TRAP_ALL U(0x2) |
| 204 | #define CPACR_EL1_FP_TRAP_NONE U(0x3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 205 | |
| 206 | /* SCR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 207 | #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) |
| 208 | #define SCR_TWE_BIT (U(1) << 13) |
| 209 | #define SCR_TWI_BIT (U(1) << 12) |
| 210 | #define SCR_ST_BIT (U(1) << 11) |
| 211 | #define SCR_RW_BIT (U(1) << 10) |
| 212 | #define SCR_SIF_BIT (U(1) << 9) |
| 213 | #define SCR_HCE_BIT (U(1) << 8) |
| 214 | #define SCR_SMD_BIT (U(1) << 7) |
| 215 | #define SCR_EA_BIT (U(1) << 3) |
| 216 | #define SCR_FIQ_BIT (U(1) << 2) |
| 217 | #define SCR_IRQ_BIT (U(1) << 1) |
| 218 | #define SCR_NS_BIT (U(1) << 0) |
| 219 | #define SCR_VALID_BIT_MASK U(0x2f8f) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 220 | #define SCR_RESET_VAL SCR_RES1_BITS |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 221 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 222 | /* MDCR_EL3 definitions */ |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 223 | #define MDCR_SPD32(x) ((x) << 14) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 224 | #define MDCR_SPD32_LEGACY U(0x0) |
| 225 | #define MDCR_SPD32_DISABLE U(0x2) |
| 226 | #define MDCR_SPD32_ENABLE U(0x3) |
| 227 | #define MDCR_SDD_BIT (U(1) << 16) |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 228 | #define MDCR_NSPB(x) ((x) << 12) |
| 229 | #define MDCR_NSPB_EL1 U(0x3) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 230 | #define MDCR_TDOSA_BIT (U(1) << 10) |
| 231 | #define MDCR_TDA_BIT (U(1) << 9) |
| 232 | #define MDCR_TPM_BIT (U(1) << 6) |
| 233 | #define MDCR_EL3_RESET_VAL U(0x0) |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 234 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 235 | #if !ERROR_DEPRECATED |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 236 | #define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 237 | #endif |
| 238 | |
| 239 | /* MDCR_EL2 definitions */ |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 240 | #define MDCR_EL2_TPMS (U(1) << 14) |
| 241 | #define MDCR_EL2_E2PB(x) ((x) << 12) |
| 242 | #define MDCR_EL2_E2PB_EL1 U(0x3) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 243 | #define MDCR_EL2_TDRA_BIT (U(1) << 11) |
| 244 | #define MDCR_EL2_TDOSA_BIT (U(1) << 10) |
| 245 | #define MDCR_EL2_TDA_BIT (U(1) << 9) |
| 246 | #define MDCR_EL2_TDE_BIT (U(1) << 8) |
| 247 | #define MDCR_EL2_HPME_BIT (U(1) << 7) |
| 248 | #define MDCR_EL2_TPM_BIT (U(1) << 6) |
| 249 | #define MDCR_EL2_TPMCR_BIT (U(1) << 5) |
| 250 | #define MDCR_EL2_RESET_VAL U(0x0) |
| 251 | |
| 252 | /* HSTR_EL2 definitions */ |
| 253 | #define HSTR_EL2_RESET_VAL U(0x0) |
| 254 | #define HSTR_EL2_T_MASK U(0xff) |
| 255 | |
| 256 | /* CNTHP_CTL_EL2 definitions */ |
| 257 | #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) |
| 258 | #define CNTHP_CTL_RESET_VAL U(0x0) |
| 259 | |
| 260 | /* VTTBR_EL2 definitions */ |
| 261 | #define VTTBR_RESET_VAL ULL(0x0) |
| 262 | #define VTTBR_VMID_MASK ULL(0xff) |
| 263 | #define VTTBR_VMID_SHIFT U(48) |
| 264 | #define VTTBR_BADDR_MASK ULL(0xffffffffffff) |
| 265 | #define VTTBR_BADDR_SHIFT U(0) |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 266 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 267 | /* HCR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 268 | #define HCR_RW_SHIFT U(31) |
| 269 | #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) |
| 270 | #define HCR_AMO_BIT (U(1) << 5) |
| 271 | #define HCR_IMO_BIT (U(1) << 4) |
| 272 | #define HCR_FMO_BIT (U(1) << 3) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 273 | |
Gerald Lejeune | 851dc7e | 2016-03-22 11:11:46 +0100 | [diff] [blame] | 274 | /* ISR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 275 | #define ISR_A_SHIFT U(8) |
| 276 | #define ISR_I_SHIFT U(7) |
| 277 | #define ISR_F_SHIFT U(6) |
Gerald Lejeune | 851dc7e | 2016-03-22 11:11:46 +0100 | [diff] [blame] | 278 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 279 | /* CNTHCTL_EL2 definitions */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 280 | #define CNTHCTL_RESET_VAL U(0x0) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 281 | #define EVNTEN_BIT (U(1) << 2) |
| 282 | #define EL1PCEN_BIT (U(1) << 1) |
| 283 | #define EL1PCTEN_BIT (U(1) << 0) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 284 | |
| 285 | /* CNTKCTL_EL1 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 286 | #define EL0PTEN_BIT (U(1) << 9) |
| 287 | #define EL0VTEN_BIT (U(1) << 8) |
| 288 | #define EL0PCTEN_BIT (U(1) << 0) |
| 289 | #define EL0VCTEN_BIT (U(1) << 1) |
| 290 | #define EVNTEN_BIT (U(1) << 2) |
| 291 | #define EVNTDIR_BIT (U(1) << 3) |
| 292 | #define EVNTI_SHIFT U(4) |
| 293 | #define EVNTI_MASK U(0xf) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 294 | |
| 295 | /* CPTR_EL3 definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 296 | #define TCPAC_BIT (U(1) << 31) |
| 297 | #define TTA_BIT (U(1) << 20) |
| 298 | #define TFP_BIT (U(1) << 10) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 299 | #define CPTR_EL3_RESET_VAL U(0x0) |
| 300 | |
| 301 | /* CPTR_EL2 definitions */ |
| 302 | #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) |
| 303 | #define CPTR_EL2_TCPAC_BIT (U(1) << 31) |
| 304 | #define CPTR_EL2_TTA_BIT (U(1) << 20) |
| 305 | #define CPTR_EL2_TFP_BIT (U(1) << 10) |
| 306 | #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 307 | |
| 308 | /* CPSR/SPSR definitions */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 309 | #define DAIF_FIQ_BIT (U(1) << 0) |
| 310 | #define DAIF_IRQ_BIT (U(1) << 1) |
| 311 | #define DAIF_ABT_BIT (U(1) << 2) |
| 312 | #define DAIF_DBG_BIT (U(1) << 3) |
| 313 | #define SPSR_DAIF_SHIFT U(6) |
| 314 | #define SPSR_DAIF_MASK U(0xf) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 315 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 316 | #define SPSR_AIF_SHIFT U(6) |
| 317 | #define SPSR_AIF_MASK U(0x7) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 318 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 319 | #define SPSR_E_SHIFT U(9) |
| 320 | #define SPSR_E_MASK U(0x1) |
| 321 | #define SPSR_E_LITTLE U(0x0) |
| 322 | #define SPSR_E_BIG U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 323 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 324 | #define SPSR_T_SHIFT U(5) |
| 325 | #define SPSR_T_MASK U(0x1) |
| 326 | #define SPSR_T_ARM U(0x0) |
| 327 | #define SPSR_T_THUMB U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 328 | |
| 329 | #define DISABLE_ALL_EXCEPTIONS \ |
| 330 | (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) |
| 331 | |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 332 | /* |
| 333 | * RMR_EL3 definitions |
| 334 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 335 | #define RMR_EL3_RR_BIT (U(1) << 1) |
| 336 | #define RMR_EL3_AA64_BIT (U(1) << 0) |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 337 | |
| 338 | /* |
| 339 | * HI-VECTOR address for AArch32 state |
| 340 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 341 | #define HI_VECTOR_BASE U(0xFFFF0000) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 342 | |
| 343 | /* |
| 344 | * TCR defintions |
| 345 | */ |
Antonio Nino Diaz | f94e40d | 2017-09-14 15:57:44 +0100 | [diff] [blame] | 346 | #define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23)) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 347 | #define TCR_EL1_IPS_SHIFT U(32) |
| 348 | #define TCR_EL3_PS_SHIFT U(16) |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 349 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 350 | #define TCR_TxSZ_MIN U(16) |
| 351 | #define TCR_TxSZ_MAX U(39) |
Antonio Nino Diaz | d48ae61 | 2016-08-02 09:21:41 +0100 | [diff] [blame] | 352 | |
Lin Ma | 741a382 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 353 | /* (internal) physical address size bits in EL3/EL1 */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 354 | #define TCR_PS_BITS_4GB U(0x0) |
| 355 | #define TCR_PS_BITS_64GB U(0x1) |
| 356 | #define TCR_PS_BITS_1TB U(0x2) |
| 357 | #define TCR_PS_BITS_4TB U(0x3) |
| 358 | #define TCR_PS_BITS_16TB U(0x4) |
| 359 | #define TCR_PS_BITS_256TB U(0x5) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 360 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 361 | #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) |
| 362 | #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) |
| 363 | #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) |
| 364 | #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) |
| 365 | #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) |
| 366 | #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 367 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 368 | #define TCR_RGN_INNER_NC (U(0x0) << 8) |
| 369 | #define TCR_RGN_INNER_WBA (U(0x1) << 8) |
| 370 | #define TCR_RGN_INNER_WT (U(0x2) << 8) |
| 371 | #define TCR_RGN_INNER_WBNA (U(0x3) << 8) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 372 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 373 | #define TCR_RGN_OUTER_NC (U(0x0) << 10) |
| 374 | #define TCR_RGN_OUTER_WBA (U(0x1) << 10) |
| 375 | #define TCR_RGN_OUTER_WT (U(0x2) << 10) |
| 376 | #define TCR_RGN_OUTER_WBNA (U(0x3) << 10) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 377 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 378 | #define TCR_SH_NON_SHAREABLE (U(0x0) << 12) |
| 379 | #define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12) |
| 380 | #define TCR_SH_INNER_SHAREABLE (U(0x3) << 12) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 381 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 382 | #define TCR_TG0_SHIFT U(14) |
| 383 | #define TCR_TG0_MASK U(3) |
| 384 | #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) |
| 385 | #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) |
| 386 | #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) |
| 387 | |
| 388 | #define TCR_EPD0_BIT (U(1) << 7) |
Antonio Nino Diaz | c8274a8 | 2017-09-15 10:30:34 +0100 | [diff] [blame] | 389 | #define TCR_EPD1_BIT (U(1) << 23) |
| 390 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 391 | #define MODE_SP_SHIFT U(0x0) |
| 392 | #define MODE_SP_MASK U(0x1) |
| 393 | #define MODE_SP_EL0 U(0x0) |
| 394 | #define MODE_SP_ELX U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 395 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 396 | #define MODE_RW_SHIFT U(0x4) |
| 397 | #define MODE_RW_MASK U(0x1) |
| 398 | #define MODE_RW_64 U(0x0) |
| 399 | #define MODE_RW_32 U(0x1) |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 400 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 401 | #define MODE_EL_SHIFT U(0x2) |
| 402 | #define MODE_EL_MASK U(0x3) |
| 403 | #define MODE_EL3 U(0x3) |
| 404 | #define MODE_EL2 U(0x2) |
| 405 | #define MODE_EL1 U(0x1) |
| 406 | #define MODE_EL0 U(0x0) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 407 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 408 | #define MODE32_SHIFT U(0) |
| 409 | #define MODE32_MASK U(0xf) |
| 410 | #define MODE32_usr U(0x0) |
| 411 | #define MODE32_fiq U(0x1) |
| 412 | #define MODE32_irq U(0x2) |
| 413 | #define MODE32_svc U(0x3) |
| 414 | #define MODE32_mon U(0x6) |
| 415 | #define MODE32_abt U(0x7) |
| 416 | #define MODE32_hyp U(0xa) |
| 417 | #define MODE32_und U(0xb) |
| 418 | #define MODE32_sys U(0xf) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 419 | |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 420 | #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) |
| 421 | #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) |
| 422 | #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) |
| 423 | #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 424 | |
Vikram Kanigiri | 9851e42 | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 425 | #define SPSR_64(el, sp, daif) \ |
| 426 | (MODE_RW_64 << MODE_RW_SHIFT | \ |
| 427 | ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ |
| 428 | ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ |
| 429 | ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) |
| 430 | |
| 431 | #define SPSR_MODE32(mode, isa, endian, aif) \ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 432 | ((MODE_RW_32 << MODE_RW_SHIFT) | \ |
| 433 | (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ |
| 434 | (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ |
| 435 | (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ |
| 436 | (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 437 | |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 438 | /* |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 439 | * TTBR Definitions |
| 440 | */ |
| 441 | #define TTBR_CNP_BIT 0x1 |
| 442 | |
| 443 | /* |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 444 | * CTR_EL0 definitions |
| 445 | */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 446 | #define CTR_CWG_SHIFT U(24) |
| 447 | #define CTR_CWG_MASK U(0xf) |
| 448 | #define CTR_ERG_SHIFT U(20) |
| 449 | #define CTR_ERG_MASK U(0xf) |
| 450 | #define CTR_DMINLINE_SHIFT U(16) |
| 451 | #define CTR_DMINLINE_MASK U(0xf) |
| 452 | #define CTR_L1IP_SHIFT U(14) |
| 453 | #define CTR_L1IP_MASK U(0x3) |
| 454 | #define CTR_IMINLINE_SHIFT U(0) |
| 455 | #define CTR_IMINLINE_MASK U(0xf) |
Dan Handley | 0cdebbd | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 456 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 457 | #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 458 | |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 459 | /* Physical timer control register bit fields shifts and masks */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 460 | #define CNTP_CTL_ENABLE_SHIFT U(0) |
| 461 | #define CNTP_CTL_IMASK_SHIFT U(1) |
| 462 | #define CNTP_CTL_ISTATUS_SHIFT U(2) |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 463 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 464 | #define CNTP_CTL_ENABLE_MASK U(1) |
| 465 | #define CNTP_CTL_IMASK_MASK U(1) |
| 466 | #define CNTP_CTL_ISTATUS_MASK U(1) |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 467 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 468 | #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 469 | CNTP_CTL_ENABLE_MASK) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 470 | #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 471 | CNTP_CTL_IMASK_MASK) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 472 | #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 473 | CNTP_CTL_ISTATUS_MASK) |
| 474 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 475 | #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) |
| 476 | #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 477 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 478 | #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) |
| 479 | #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) |
Achin Gupta | 405406d | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 480 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 481 | /* Exception Syndrome register bits and bobs */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 482 | #define ESR_EC_SHIFT U(26) |
| 483 | #define ESR_EC_MASK U(0x3f) |
| 484 | #define ESR_EC_LENGTH U(6) |
| 485 | #define EC_UNKNOWN U(0x0) |
| 486 | #define EC_WFE_WFI U(0x1) |
| 487 | #define EC_AARCH32_CP15_MRC_MCR U(0x3) |
| 488 | #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) |
| 489 | #define EC_AARCH32_CP14_MRC_MCR U(0x5) |
| 490 | #define EC_AARCH32_CP14_LDC_STC U(0x6) |
| 491 | #define EC_FP_SIMD U(0x7) |
| 492 | #define EC_AARCH32_CP10_MRC U(0x8) |
| 493 | #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) |
| 494 | #define EC_ILLEGAL U(0xe) |
| 495 | #define EC_AARCH32_SVC U(0x11) |
| 496 | #define EC_AARCH32_HVC U(0x12) |
| 497 | #define EC_AARCH32_SMC U(0x13) |
| 498 | #define EC_AARCH64_SVC U(0x15) |
| 499 | #define EC_AARCH64_HVC U(0x16) |
| 500 | #define EC_AARCH64_SMC U(0x17) |
| 501 | #define EC_AARCH64_SYS U(0x18) |
| 502 | #define EC_IABORT_LOWER_EL U(0x20) |
| 503 | #define EC_IABORT_CUR_EL U(0x21) |
| 504 | #define EC_PC_ALIGN U(0x22) |
| 505 | #define EC_DABORT_LOWER_EL U(0x24) |
| 506 | #define EC_DABORT_CUR_EL U(0x25) |
| 507 | #define EC_SP_ALIGN U(0x26) |
| 508 | #define EC_AARCH32_FP U(0x28) |
| 509 | #define EC_AARCH64_FP U(0x2c) |
| 510 | #define EC_SERROR U(0x2f) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 511 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 512 | #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 513 | |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 514 | /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 515 | #define RMR_RESET_REQUEST_SHIFT U(0x1) |
| 516 | #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 517 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 518 | /******************************************************************************* |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 519 | * Definitions of register offsets, fields and macros for CPU system |
| 520 | * instructions. |
| 521 | ******************************************************************************/ |
| 522 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 523 | #define TLBI_ADDR_SHIFT U(12) |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 524 | #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) |
| 525 | #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) |
| 526 | |
| 527 | /******************************************************************************* |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 528 | * Definitions of register offsets and fields in the CNTCTLBase Frame of the |
| 529 | * system level implementation of the Generic Timer. |
| 530 | ******************************************************************************/ |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 531 | #define CNTNSAR U(0x4) |
| 532 | #define CNTNSAR_NS_SHIFT(x) (x) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 533 | |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 534 | #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) |
| 535 | #define CNTACR_RPCT_SHIFT U(0x0) |
| 536 | #define CNTACR_RVCT_SHIFT U(0x1) |
| 537 | #define CNTACR_RFRQ_SHIFT U(0x2) |
| 538 | #define CNTACR_RVOFF_SHIFT U(0x3) |
| 539 | #define CNTACR_RWVT_SHIFT U(0x4) |
| 540 | #define CNTACR_RWPT_SHIFT U(0x5) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 541 | |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 542 | /* PMCR_EL0 definitions */ |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 543 | #define PMCR_EL0_RESET_VAL U(0x0) |
Varun Wadekar | c6a11f6 | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 544 | #define PMCR_EL0_N_SHIFT U(11) |
| 545 | #define PMCR_EL0_N_MASK U(0x1f) |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 546 | #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) |
David Cunado | 4168f2f | 2017-10-02 17:41:39 +0100 | [diff] [blame] | 547 | #define PMCR_EL0_LC_BIT (U(1) << 6) |
| 548 | #define PMCR_EL0_DP_BIT (U(1) << 5) |
| 549 | #define PMCR_EL0_X_BIT (U(1) << 4) |
| 550 | #define PMCR_EL0_D_BIT (U(1) << 3) |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 551 | |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 552 | /******************************************************************************* |
| 553 | * Definitions of MAIR encodings for device and normal memory |
| 554 | ******************************************************************************/ |
| 555 | /* |
| 556 | * MAIR encodings for device memory attributes. |
| 557 | */ |
| 558 | #define MAIR_DEV_nGnRnE ULL(0x0) |
| 559 | #define MAIR_DEV_nGnRE ULL(0x4) |
| 560 | #define MAIR_DEV_nGRE ULL(0x8) |
| 561 | #define MAIR_DEV_GRE ULL(0xc) |
| 562 | |
| 563 | /* |
| 564 | * MAIR encodings for normal memory attributes. |
| 565 | * |
| 566 | * Cache Policy |
| 567 | * WT: Write Through |
| 568 | * WB: Write Back |
| 569 | * NC: Non-Cacheable |
| 570 | * |
| 571 | * Transient Hint |
| 572 | * NTR: Non-Transient |
| 573 | * TR: Transient |
| 574 | * |
| 575 | * Allocation Policy |
| 576 | * RA: Read Allocate |
| 577 | * WA: Write Allocate |
| 578 | * RWA: Read and Write Allocate |
| 579 | * NA: No Allocation |
| 580 | */ |
| 581 | #define MAIR_NORM_WT_TR_WA ULL(0x1) |
| 582 | #define MAIR_NORM_WT_TR_RA ULL(0x2) |
| 583 | #define MAIR_NORM_WT_TR_RWA ULL(0x3) |
| 584 | #define MAIR_NORM_NC ULL(0x4) |
| 585 | #define MAIR_NORM_WB_TR_WA ULL(0x5) |
| 586 | #define MAIR_NORM_WB_TR_RA ULL(0x6) |
| 587 | #define MAIR_NORM_WB_TR_RWA ULL(0x7) |
| 588 | #define MAIR_NORM_WT_NTR_NA ULL(0x8) |
| 589 | #define MAIR_NORM_WT_NTR_WA ULL(0x9) |
| 590 | #define MAIR_NORM_WT_NTR_RA ULL(0xa) |
| 591 | #define MAIR_NORM_WT_NTR_RWA ULL(0xb) |
| 592 | #define MAIR_NORM_WB_NTR_NA ULL(0xc) |
| 593 | #define MAIR_NORM_WB_NTR_WA ULL(0xd) |
| 594 | #define MAIR_NORM_WB_NTR_RA ULL(0xe) |
| 595 | #define MAIR_NORM_WB_NTR_RWA ULL(0xf) |
| 596 | |
| 597 | #define MAIR_NORM_OUTER_SHIFT 4 |
| 598 | |
| 599 | #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) |
| 600 | |
Jeenu Viswambharan | 1dc771b | 2017-10-19 09:15:15 +0100 | [diff] [blame] | 601 | /* PAR_EL1 fields */ |
| 602 | #define PAR_F_SHIFT 0 |
| 603 | #define PAR_F_MASK 1 |
| 604 | #define PAR_ADDR_SHIFT 12 |
| 605 | #define PAR_ADDR_MASK (BIT(40) - 1) /* 40-bits-wide page address */ |
| 606 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 607 | #endif /* __ARCH_H__ */ |